SLLS902 Data sheet

SLLS902A February 2010 – March 2024 SN65MLVD040

PRODUCTION DATA

5.9 Driver Switching Characterisitics

over recommended operating conditions unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
t_pLH	Propagation delay time, low-to-high-level output	See Figure 6-5	1.3	1.9	2.4	ns
t_pHL	Propagation delay time, high-to-low-level output		1.3	1.9	2.4	ns
t_r	Differential output signal rise time		0.9		2	ns
t_f	Differential output signal fall time		0.9		2.2	ns
t_sk(o)	Output skew				200	ps
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)				150	ps
t_sk(pp)	Part-to-part skew ⁽²⁾				300	ps
t_jit(per)	Period jitter, rms (1 standard deviation)⁽³⁾	All channels switching, 125 MHz clock input⁽⁴⁾, see Figure 6-8			2	ps
t_jit(c-c)	Cycle-to-cycle jitter, rms⁽³⁾				9	ps
t_jit(det)	Deterministic jitter⁽³⁾	All channels switching, 250 Mbps 2¹⁵–1 PRBS input⁽⁴⁾, see Figure 6-8			290	ps
t_jit(r)	Random jitter⁽³⁾				4	ps
t_PZH	Enable time, high-impedance-to-high-level output	See Figure 6-6			7	ns
t_PZL	Enable time, high-impedance-to-low-level output				7	ns
t_PHZ	Disable time, high-level-to-high-impedance output				7	ns
t_PLZ	Disable time, low-level-to-high-impedance output				7	ns

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) t_sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4) t_r = t_f = 0.5 ns (10% to 90%)