SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.5 Register Maps

The DPHY440 local I2C interface is enabled when RSTN is input high. Access to the CSR registers is supported during ultra-low power state (ULPS). The EQ/SCL and ERC/SDA terminals are used for I2C clock and I2C data respectively. The DPHY440 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000) and supports up to 100 kHz.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for DPHY440 is factory preset to 1101100.

Table 4. DPHY440 I2C Target Address Description

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W/R)
1 1 0 1 1 0 0 0/1
Address Cycle is 0xD8 (Write) and 0xD9 (Read)

The following procedure should be followed to write to the DPHY440 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The DPHY440 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of data, MSB-first
  4. The DPHY440 acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The DPHY440 acknowledges the byte transfer.
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the DPHY440.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the DPHY440 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the DPHY440 7-bit address and a one-value “W/R” bit to indicate a read cycle
  2. The DPHY440 acknowledges the address cycle.
  3. The DPHY440 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the DPHY440 I2C register occurred prior to the read, then the DPHY440 starts at the sub-address specified in the write.
  4. The DPHY440 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the DPHY440 transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The DPHY440 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of data, MSB-first.
  4. The DPHY440 acknowledges the sub-address cycle.
  5. The master terminates the write operation by generating a stop condition (P).

NOTE

If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. If a I2C write occurred prior to the read, then the reads start at the sub-address specified by the write.