SLLSEO9C March 2016 – August 2019 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | HSTX_VSADJ | Reserved | HSTX_PRE | ||||
R | R | RW | RW | R | R | RW | RW |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | Reserved | R | Reserved | |
5:4 | HSTX_VSADJ | RWU | 0 | This field controls the HS TX voltage swing level. The value of this field will match the sampled state of the CFG[1:0] pins. Software can change the value of this field at a later time.
00 – 180 mV 01 – 200 mV (CFG0 = VIM or (CFG0 = VIL and !CFG1 = VIH)) 1X – 220mV (CFG0 = VIH or (CFG0 = VIL and CFG1 = VIH)) |
3:2 | Reserved | R | Reserved | |
1:0 | HSTX_PRE | RWU | 0 | This field controls the HS TX pre-emphasis level. The value of this field will match the sampled state of CFG1 pin. Software can change the value of this field at a later time.
00 – 1.5 dB 01 – 0 dB (CFG1 = VIM or VIL) 1X – 2.5 dB (CFG1 = VIH) |