SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
I2C (ERC (SDA), EQ (SCL))
F(SCL) I2C Clock Freqency 100 kHz
tF_I2C Fall time of both SDA and SCL signals Load of 350 pF with 2-K pullup resistor.
Measure at 30% - 70%		 300 ns
tR_I2C Rise Time of both SDA and SCL signals 1000 ns
DPHY LINK
F(BR) Bit Rate 1.5 Gbps
F(HSCLK) HS Clock Input range 100 750 MHz
F(DESKEW) Automatic Deskew range 220 750 MHz
MIPI DPHY HS Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)
∆V(CMRX_HF) Common-mode Interface beyond 450 MHz 100 mV
∆V(CMRX_LF) Common-mode interference 50 MHz – 450 MHz –50 50 mV
MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)
∆V(CMRX_HF) Common-level variations above 450 MHz 5 mVrms
∆V(CMRX_LF) Common-level variation between 50 MHz – 450 MHz. 25 mVpeak
tR and tF 20% - 80% rise time and fall time Datarate ≤ 1 Gbps 0.3 UI
Datarate > 1 Gbps 0.35 UI
100 ps
MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)
eSPIKE Input Pulse rejection 300 V ps
tMIN(RX) Minimum pulse width response 20 ns
V(INT) Peak interference amplitude 200 mv
F(INT) Interference Frequency 450 Mhz
t(LP-PULSE-RX) Pulse Width of the XOR of DAxP and DAxN First LP XOR clock pulse after Stop state or last pulse before Stop state. 42 ns
All other pulses. 22 ns
MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)
tREOT 30% - 85% rise time and fall time Measured at end of HS transmission. 35 ns
t(LP-PULSE-TX) Pulse Width of the LP XOR clock First LP XOR clock pulse after Stop state or last pulse before Stop state 40 ns
All other pulses 20 ns
t(LP-PER-TX) Period of the LP XOR clock 90 ns
δV/δtsr Slew Rate at CLOAD = 70 pF 150 mV/ns
Slew Rate at CLOAD = 0 pF Fallng edge only 30 mV/ns
Slew Rate at CLOAD = 0 pF Rising edge only 30 mV/ns
CLOAD Load Capacitance 70 pF
(1) (1) All typical values are at VCC = 3.3 V, and TA = 25°C.
SN65DPHY440SS SN75DPHY440SS i2c_timing_sllseo9.gifFigure 1. I2C Timing
SN65DPHY440SS SN75DPHY440SS td_01_dphy_hs_rx_tx_sllseo9.gifFigure 2. DPHY HS RX and TX Timing
SN65DPHY440SS SN75DPHY440SS td_02_dphy_hs_tx_pre_emph_sllseo9.gifFigure 3. DPHY HS TX Pre-emphasis