SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.7 Timing Requirements

MIN NOM MAX UNIT
I2C (ERC (SDA), EQ (SCL))
tHD;STA Hold Time (repeated) START condition. After this period, the first clock pulse is generated 4 µs
tLOW Low period of SCL clock 4.7 µs
tHIGH High period of SCL clock 4 µs
tSU;STA Setup time for a repeated START condition 4.7 µs
tHD;DAT Data hold time 5 µs
tSU;DAT Data setup time 4 µs
tSU;STO Setup time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
MIPI DPHY HS Interface
tHSPD Propagation delay from DA to DB. 4 + 12ns 4 + 40ns UI
tDBC_DCYCLE DAC to DBC output duty cycle distortion percentage 750 MHz clock with 50%-50% duty cycle at DAC input. –5 5 %
tSKEW-TX-1G Data to Clock variation from 0.5UI. Refer to Figure 2 Datarate ≤ 1 Gbps –0.1 0.1 UI
tSETUP-RX-1G Data to Clock setup time. Refer to Figure 2 Datarate ≤ 1 Gbps 0.1 UI
tHOLD-RX-1G Clock to data hold time. Refer to Figure 2 Datarate ≤ 1 Gbps 0.1 UI
tSKEW-TX-1P5G Data to Clock variation from 0.5UI. Refer to Figure 2 Datarate > 1 Gbps –0.15 0.15 UI
tSETUP-RX-1P5G Data to Clock setup time. Refer to Figure 2 Datarate > 1 Gbps 0.15 UI
tHOLD-RX-1P5G Clock to data hold time. Refer to Figure 2 Datarate > 1 Gbps 0.15 UI