SLOA011B January   2018  – July 2021 LF347 , LF353 , LM348 , MC1458 , TL022 , TL061 , TL062 , TL071 , TL072 , UA741

 

  1. 1Introduction
    1. 1.1 Amplifier Basics
    2. 1.2 Ideal Op Amp Model
  2. 2Non-Inverting Amplifier
    1. 2.1 Closed Loop Concepts and Simplifications
  3. 3Inverting Amplifier
    1. 3.1 Closed Loop Concepts and Simplifications
  4. 4Simplified Op Amp Circuit Diagram
    1. 4.1 Input Stage
    2. 4.2 Second Stage
    3. 4.3 Output Stage
  5. 5Op Amp Specifications
    1. 5.1  Absolute Maximum Ratings and Recommended Operating Condition
    2. 5.2  Input Offset Voltage
    3. 5.3  Input Current
    4. 5.4  Input Common Mode Voltage Range
    5. 5.5  Differential Input Voltage Range
    6. 5.6  Maximum Output Voltage Swing
    7. 5.7  Large Signal Differential Voltage Amplification
    8. 5.8  Input Parasitic Elements
      1. 5.8.1 Input Capacitance
      2. 5.8.2 Input Resistance
    9. 5.9  Output Impedance
    10. 5.10 Common-Mode Rejection Ratio
    11. 5.11 Supply Voltage Rejection Ratio
    12. 5.12 Supply Current
    13. 5.13 Slew Rate at Unity Gain
    14. 5.14 Equivalent Input Noise
    15. 5.15 Total Harmonic Distortion Plus Noise
    16. 5.16 Unity-Gain Bandwidth and Phase Margin
    17. 5.17 Settling Time
  6. 6References
  7. 7Glossary
  8. 8Revision History

5.8 Input Parasitic Elements

Both inputs have parasitic impedance associated with them. Figure 5-6 shows a model where it is lumped into resistance and capacitance between each input terminal and ground and between the two terminals. There is also parasitic inductance, but the effects are negligible at low frequency.

Input impedance is a design issue when the source impedance is high. The input loads the source.

Also input capacitance will cause extra phase shift in the feedback path. This erodes phase margin and can be a problem when using high value feedback resistors.

GUID-0BFAAF98-C7D6-42C6-8294-7A8DBC790822-low.gifFigure 5-6 Input Parasitic Elements