SLOA011B January   2018  – July 2021 LF347 , LF353 , LM348 , MC1458 , TL022 , TL061 , TL062 , TL071 , TL072 , UA741

 

  1. 1Introduction
    1. 1.1 Amplifier Basics
    2. 1.2 Ideal Op Amp Model
  2. 2Non-Inverting Amplifier
    1. 2.1 Closed Loop Concepts and Simplifications
  3. 3Inverting Amplifier
    1. 3.1 Closed Loop Concepts and Simplifications
  4. 4Simplified Op Amp Circuit Diagram
    1. 4.1 Input Stage
    2. 4.2 Second Stage
    3. 4.3 Output Stage
  5. 5Op Amp Specifications
    1. 5.1  Absolute Maximum Ratings and Recommended Operating Condition
    2. 5.2  Input Offset Voltage
    3. 5.3  Input Current
    4. 5.4  Input Common Mode Voltage Range
    5. 5.5  Differential Input Voltage Range
    6. 5.6  Maximum Output Voltage Swing
    7. 5.7  Large Signal Differential Voltage Amplification
    8. 5.8  Input Parasitic Elements
      1. 5.8.1 Input Capacitance
      2. 5.8.2 Input Resistance
    9. 5.9  Output Impedance
    10. 5.10 Common-Mode Rejection Ratio
    11. 5.11 Supply Voltage Rejection Ratio
    12. 5.12 Supply Current
    13. 5.13 Slew Rate at Unity Gain
    14. 5.14 Equivalent Input Noise
    15. 5.15 Total Harmonic Distortion Plus Noise
    16. 5.16 Unity-Gain Bandwidth and Phase Margin
    17. 5.17 Settling Time
  6. 6References
  7. 7Glossary
  8. 8Revision History

5.5 Differential Input Voltage Range

Differential input voltage range is normally specified in data sheets as an absolute maximum. Figure 5-4 illustrates this.

If the differential input voltage is greater than the base-emitter reverse break down voltage of input transistor Q1 plus the baseemitter forward breakdown voltage of Q2, then Q1’s BE junction will act like a zener diode. This is a destructive mode of operation and results in deterioration of Q1’s current gain. The same is true if VIN_DIFF is reversed, except Q2 breaks down.

GUID-80E812E2-DF9C-47F4-AC52-5640F498EAD9-low.gifFigure 5-4 Differential-Mode Voltage Input Limit

Some devices have protection built into them, and the current into the input needs to be limited. Normally, differential input mode voltage limit is not a design issue.