SLOA349 March   2025 TAS6584-Q1 , TAS6684-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2SDOUT Configuration
    1. 2.1 SDOUT – I2S Configuration
    2. 2.2 SDOUT – TDM Configuration
  6. 3SDOUT Connection in Multi-Device System
  7. 4Output Current and Voltage Calculation
  8. 5Summary
  9. 6References

3 SDOUT Connection in Multi-Device System

Each SDOUT pin only can transmit one device measurement data. In multi-device systems, multiple devices SDOUTs data can share one TDM line can save DSP/SOC pins and resources. The SDOUT pin is a tri-state (0, 1, Hi-Z) output pin. Multiple SDOUT pins can be tied together directly. In multi-device systems the offset must be used to shift data groups to available slots and allow multiple devices to share one TDM line. The recommendation is to synchronize multiple devices through SCLK as Figure 3-1. To avoid SDOUT delay which caused by SCLK layout trace on PCB board, SCLK synchronization can be configured by register 0x60. The setup sequence is as follows:

  1. Halt the Audio input Serial clock (SCLK). The I2C communication remains enabled
  2. In register RAMP_PHASE_CTRL0 (Address = 0x60)
    • Set the reg_phase_sync_en bit to “1” to enable phase sync function
    • Set reg_phase_sync_sel bit to “1” to enable internal sync
  3. Select the output phase settings for each device and the respective channels
    • Manual phase mode can optionally be used to select preferable output channel phase offsets across all channels in the systems. More details can be found in High-Frequency Pulse-Width Modulator (PWM)
  4. Set all channels on each synchronized device to Hi-Z state
  5. Provide the Audio input Serial clock (SCLK) and wait a minimum of 2ms before proceeding to the next step
  6. Set each channel to PLAY state
SCLK Synchronization architecture and SDOUT connection Figure 3-1 SCLK Synchronization architecture and SDOUT connection

Table 3-1 and Figure 3-2 are the SDOUT configuration and timing diagram example of four TAS6x84-Q1 devices in TDM16 mode. Each device only enables four channels of current sense output. The four SDOUT1 pins are tied together.

Table 3-1 SDOUT – TDM16 Configuration Example
Register 0x25, bit[7:4] Register 0x31, bit[3:0] Register 0x2C Register 0x2D Register 0x2E Register 0x2F Pin Slot 1-4 Slot 5-8 Slot 9-12 Slot 13-16
Device 1 0000 0010 0xCF 0xFF 0x00 0xFF SDOUT1 Isense Ch1-4 - - -
Device 2 0000 0010 0xCF 0xFF 0x80 0xFF SDOUT1 - Isense Ch1-4 - -
Device 3 0000 0010 0xDF 0xFF 0x00 0xFF SDOUT1 - - Isense Ch1-4 -
Device 4 0000 0010 0xDF 0xFF 0x80 0xFF SDOUT1 - - - Isense Ch1-4
Timing Diagram Example for SDOUT in TDM8 Configuration Figure 3-2 Timing Diagram Example for SDOUT in TDM8 Configuration

The following are SDOUT configuration PPC3 script for the four devices.

Note: The four I2C addresses need to be adjusted accordingly.
### Device 1 SDOUT configuration script  ####
w c0 60 03          # sync devices through SCLK
w c0 20 10          # configure SCLK to inverted mode if SCLK is 24.576MHz
w c0 25 0F          # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32          # 32 bit length for Aux
w c0 31 02          # enable Ch1/2/3/4 Isense output.
w c0 2C CF          # MSB offset of Vpredict, Isense and Aux
w c0 2D FF          # Vpredict LSB offset, work with 0x2C register to remove Vpredict out of 16 slots
w c0 2E 00          # Isense LSB offset, work with 0x2C register to place Isense on slot 1-4
w c0 2F FF          # Aux1 LSB, work with 0x2C register to remove Aux1 out of 16 slots
w c0 30 FF          # Aux2 LSB, work with 0x2C register to remove Aux2 out of 16 slots
### Device 2 SDOUT configuration script  ####
w c0 60 03          # sync devices through SCLK
w c0 20 10          # configure SCLK to inverted mode if SCLK is 24.576MHz
w c0 25 0F          # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32          # 32 bit length for Aux
w c0 31 02          # enable Ch1/2/3/4 Isense output. 
w c0 2C CF          # MSB offset of Vpredict, Isense and Aux
w c0 2D FF          # Vpredict LSB offset, work with 0x2C register to remove Vpredict out of 16 slots
w c0 2E 80          # Isense LSB offset, work with 0x2C register to place Isense on slot 5-8
w c0 2F FF          # Aux1 LSB, work with 0x2C register to remove Aux1 out of 16 slots
w c0 30 FF          # Aux2 LSB, work with 0x2C register to remove Aux2 out of 16 slots
### Device 3 SDOUT configuration script  ####
w c0 60 03          # sync devices through SCLK
w c0 20 10          # configure SCLK to inverted mode if SCLK is 24.576MHz
w c0 25 0F          # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32          # 32 bit length for Aux
w c0 31 02          # enable Ch1/2/3/4 Isense output. 
w c0 2C DF          # MSB offset of Vpredict, Isense and Aux
w c0 2D FF          # Vpredict LSB offset, work with 0x2C register to remove Vpredict out of 16 slots
w c0 2E 00          # Isense LSB offset, work with 0x2C register to place Isense on slot 9-12
w c0 2F FF          # Aux1 LSB, work with 0x2C register to remove Aux1 out of 16 slots
w c0 30 FF          # Aux2 LSB, work with 0x2C register to remove Aux2 out of 16 slots
### Device 4 SDOUT configuration script  ####
w c0 60 03         # sync devices through SCLK
w c0 20 10         # configure SCLK to inverted mode if SCLK is 24.576MHz
w c0 25 0F         # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32         # 32 bit length for Aux
w c0 31 02         # enable Ch1/2/3/4 Isense output. 
w c0 2C DF         # MSB offset of Vpredict, Isense and Aux
w c0 2D FF         # Vpredict LSB offset, work with 0x2C register to remove Vpredict out of 16 slots
w c0 2E 80         # Isense LSB offset, work with 0x2C register to place Isense on slot 13-16
w c0 2F FF         # Aux1 LSB, work with 0x2C register to remove Aux1 out of 16 slots
w c0 30 FF         # Aux2 LSB, work with 0x2C register to remove Aux2 out of 16 slots