4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS62850x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to Ground (see Table 4-2)
• Pin open-circuited (see Table 4-3)
• Pin short-circuited to an adjacent pin (see Table 4-4)
• Pin short-circuited to VIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Figure 4-1 shows the TPS62850x-Q1 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS62850x-Q1 datasheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• The device is operating in the typical application, please refer to the 'Simplified Schematics' on the 1st page in the TPS62850x-Q1 datasheet.