3 Input (V_IN) and Output (V_OUT) Voltage Sensing for UVLO and OVP Fault Protection

V_IN and V_OUT are sensed and measured across the auxiliary winding (V_AUX) that is used to provide power to the flyback controller (U1) while the transformer is being energized. Figure 3-1 shows the switching wave form of DCM flyback converter operating near critical conduction. In this figure DRV is the logic level of the flyback controllers gate driver and CS is the voltage measured across the current sense resistor (R_CS). When the transformer is being energized during the flyback FETs (Q_A) on-time (t_ON) V_IN can be measured directly across V_AUX. Refer to Equation 1, Figure 1-1, and Figure 3-1 for details.

The flyback controller can sense V_OUT while the transformer is delivering energy after the flyback converters transformer leakage spike that occurs during the T_{LK_RESET} time period has dissipated during t_DMAG. Refer to Equation 2 and Figure 1-1 for details.

To prevent false measurements of V_OUT the flyback controllers discussed in this paper have a leading edge blanking circuit. The controllers do not sense V_OUT during pre-programed blanking time (T_{LK_RESET}). T_{LK_RESET} moves with loading. For example, at full load, the UCC28704 controller will not sense V_OUT for 3 us (T_{LK_RESET}). When operating in the AM band to control the duty cycle, the transformer primary peak current adjusts linearly from I_PP to I_PP/4 to control the duty cycle. When the UCC28704 is operating in the AM band T_{LK_RESET} will be adjusted from 3 µs down to 750 ns as the primary-peak current decreases. When this occurs the flyback converter will go deeper into DCM operation. Refer to Figure 3-2 for details. Please note for this aux winding to sense the V_OUT correctly requires the aux winding signal to be as clean as possible between the end of T_{LK_RESET} and the end of t_DMAG. This will be discussed in greater detail later in this application note.