SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

1.1 Pin Configuration and Functions



Figure 1-1 DWN Package, 36-Pin SSOP (Top View)
Table 1-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
GNDP 1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. See Section 12.
/PG 3 O

Active low powergood open-drain output pin. /PG pulled low when (UVLO ≤ VIN ≤ OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); (UVP2 ≤ (COM – VEE) ≤ OVP2); TJ_Primary ≤ TSHUT_primary; and TJ_secondary ≤ TSHUT_secondary
ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum.
VIN 6, 7 P Primary input voltage. Connect a 2.2-µF ceramic capacitor from VIN to GNDP. Connect a 0.1-µF high-frequency bypass ceramic capacitor close the IC pins.
VEE 19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36 G

Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths.
VDD 28, 29 P Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins.
RLIM 32 P Secondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See Section 8.1 for more detail.
FBVEE 33 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on the top layer or back layer connected with vias.
FBVDD 34 I Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on the top layer or back layer connected with vias.
VEEA 35 G Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Section 12.
(1) P = power, G = ground, I = input, O = output