SLUS720F February   2007  – June 2019 TPS40195

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Dissipation Ratings
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable Functionality
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Oscillator and Synchronization
      4. 8.3.4  Undervoltage Lockout (UVLO)
      5. 8.3.5  Soft Start
      6. 8.3.6  Selecting the Short Circuit Threshold
      7. 8.3.7  5-V Regulator
      8. 8.3.8  Prebias Start-up
      9. 8.3.9  Drivers
      10. 8.3.10 Power Good
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Inductor, LOUT
          2. 9.2.1.2.2 Output Capacitor, COUT
          3. 9.2.1.2.3 Input Capacitor, CIN
          4. 9.2.1.2.4 Switching MOSFET, QSW
          5. 9.2.1.2.5 Rectifier MOSFET, QSR
          6. 9.2.1.2.6 Component Selection for the TPS40195
            1. 9.2.1.2.6.1 Timing Resistor, RT
            2. 9.2.1.2.6.2 Setting UVLO
            3. 9.2.1.2.6.3 Setting the Soft-Start Time
            4. 9.2.1.2.6.4 Short-Circuit Protection, RILIM
            5. 9.2.1.2.6.5 Voltage Decoupling Capacitors, CBP, and CVDD
            6. 9.2.1.2.6.6 Boost Voltage, CBOOST and DBOOST (optional)
            7. 9.2.1.2.6.7 Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1
          7. 9.2.1.2.7 Application Curve
      2. 9.2.2 Typical Application 2
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Typical Application 3
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Related Parts
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9.2.1.2.6.7 Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1

A graphical method is used to select the compensation components. This is a standard feedforward buck converter. Its PWM gain is given by the following equation.

Equation 37. TPS40195 q_kpwm_lus720.gif

The gain of the output LC filter is given in Equation 38.

Equation 38. TPS40195 q_klc_lus720.gif

The equation for the PWM and LC gain is:

Equation 39. TPS40195 q_ges_lus720.gif

To plot this on a Bode plot the DC gain must be expressed in dB. The DC gain is equal to KPWM. To express this in dB we take its LOG and multiple by 20. For this converter the DC gain is:

Equation 40. TPS40195 dcgain_lus720.gif

Also calculate the pole and zero frequencies. A double pole is associated with the LC and a zero is associated with the ESR of the output capacitance. The frequency at where these occur can be calculated using Equation 41.

Equation 41. TPS40195 flcpole_lus720.gif
Equation 42. TPS40195 fesr0_lus720.gif

A Bode plot of the PWM and LC filter is shown in Figure 23.

TPS40195 pwmlcfilter_lus720.gifFigure 23. PWM and L-C Filter Gain

A Type-III compensation network, shown in Figure 24, is used for this design. A typical bode plot of a Type-III compensation network is shown below in Figure 25.

TPS40195 newt3schem_lus720.gifFigure 24. Type III Compensation Schematic
TPS40195 type3plot_lus720.gifFigure 25. Type-III Compensation Network Typical Bode Plot

The output voltage, the high-frequency gain and the break (pole and zero) frequencies are calculated using the following equations.

Equation 43. TPS40195 q_rset_lus720.gif
Equation 44. TPS40195 q_rset02_lus720.gif
Equation 45. TPS40195 q_gain_lus720.gif
Equation 46. TPS40195 q_fp1_lus720.gif
Equation 47. TPS40195 q_fp2_lus720.gif
Equation 48. TPS40195 q_fz2_lus720.gif
Equation 49. TPS40195 q_fz2x_lus720.gif

Steps in closing the feedback loop.

  1. Place one zero well below the L-C double pole at 5.8 kHz (fZ1=2.1 kHz)
  2. Place the second zero near the double pole fZ2 at 5.8 kHz.
  3. Place one pole well above the desired cross over frequency, selected as one sixth the switching frequency, fCO1 = 50 kHz, fP1 = 300 kHz
  4. Place the second pole near the ESR zero of the output capacitors of 318 kHz. fP2 = 318 kHz
  5. The high frequency gain must be such that the over all system has 0 dB at the required crossover frequency. This gain is -1 times the sum of the modulator gain and the gain of the output stage at the crossover frequency of 50 kHz.

Using these values and the above equations calculate the setpoint and the Rs and Cs around the compensation network using the following procedure.

  1. Set RZ1 = 51 kΩ
  2. Calculate RSET using Equation 43. For this module RSET = a standard 1% value = 24.9 kΩ.
  3. Using Equation 48 and fZ1 = 1.8 kHz, CPZ1 can be calculated to be 1500 pF, FP1 and Equation 46 yields RP1 to be 363 Ω and the standard value 357 Ω is used.
  4. From Figure 23, the required gain is calculated at 15.8 dB. Equation 45 sets the value for RPZ2. A resistor for RPZ2 with value of 12.7 kΩ is used. CZ2 is calculated using Equation 49 and the desired frequency for the second zero, CZ2 = 1475 pF. A 2200 pF capacitor is used.
  5. CP2 is calculated using the second pole frequency and Equation 47, CP2 = 37 pF. A 33-pf capacitor is used.