SLUSCO1A June   2017  – April 2018 UCC27212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
      2.      Propagation Delays vs Supply Voltage T = 25°C
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
      2. 7.3.2 Undervoltage Lockout (UVLO)
      3. 7.3.3 Level Shift
      4. 7.3.4 Boot Diode
      5. 7.3.5 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS, VDD = VHB = 12 V
TDLFF VLI falling to VLO falling CLOAD = 0 10 16 30 ns
TDHFF VHI falling to VHO falling CLOAD = 0 10 16 30 ns
TDLRR VLI rising to VLO rising CLOAD = 0 10 20 42 ns
TDHRR VHI rising to VHO rising CLOAD = 0 10 20 42 ns
PROPAGATION DELAYS, VDD = VHB = 6.8 V
TDLFF VLI falling to VLO falling CLOAD = 0 10 24 50 ns
TDHFF VHI falling to VHO falling CLOAD = 0 10 24 50 ns
TDLRR VLI rising to VLO rising CLOAD = 0 13 28 57 ns
TDHRR VHI rising to VHO rising CLOAD = 0 13 28 57 ns
DELAY MATCHING, VDD = VHB = 12 V
TMON From HO OFF to LO ON TJ = 25°C 4 9.5 ns
TJ = –40°C to +140°C 4 17 ns
TMOFF From LO OFF to HO ON TJ = 25°C 4 9.5 ns
TJ = –40°C to +140°C 4 17 ns
DELAY MATCHING, VDD = VHB = 6.8 V
TMON From HO OFF to LO ON TJ = 25°C 8 ns
TJ = –40°C to +140°C 8 18 ns
TMOFF From LO OFF to HO ON TJ = 25°C 6 ns
TJ = –40°C to +140°C 6 18 ns
OUTPUT RISE AND FALL TIME, VDD = VHB = 12 V
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns
tR HO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns
tF HO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns
tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6 µs
tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.20 0.4 µs
OUTPUT RISE AND FALL TIME, VDD = VHB = 6.8 V
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 9.5 ns
tR HO rise time CLOAD = 1000 pF, from 10% to 90% 13.0 ns
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 9.5 ns
tF HO fall time CLOAD = 1000 pF, from 90% to 10% 13.0 ns
tR LO, HO CLOAD = 0.1 µF, (30% to 70%) 0.45 0.7 µs
tF LO, HO CLOAD = 0.1 µF, (70% to 30%) 0.2 0.5 µs
MISCELLANEOUS
Minimum input pulse width that changes the output 100 ns
Bootstrap diode turnoff time (1)(2) IF = 20 mA, IREV = 0.5 A (3) 20 ns
Extended output pulse when VDD = VHB = 6.8 V, VHS = 100 V, and input pulse width is 100 ns 325 ns
(1) Ensured by design.
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Typical values for TA = 25°C.
UCC27212 timing_diagram_slusco1.gifFigure 1. Timing Diagram