SLUSF65A October   2023  – January 2026 BQ25185

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Precharge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 ISET Pin Detection
        5. 7.1.1.5 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Regulation
      6. 7.3.6  ILIM/VSET Control
      7. 7.3.7  Protection Mechanisms
        1. 7.3.7.1 Input Overvoltage Protection
        2. 7.3.7.2 Battery Undervoltage Lockout
        3. 7.3.7.3 Battery Overcurrent Protection
        4. 7.3.7.4 System Overvoltage Protection
        5. 7.3.7.5 System Short Protection
        6. 7.3.7.6 Thermal Protection and Thermal Regulation
        7. 7.3.7.7 Safety Timer
      8. 7.3.8  Pushbutton Long Press Function
      9. 7.3.9  External NTC Monitoring (TS)
        1. 7.3.9.1 TS Biasing and Function
      10. 7.3.10 Status Pins
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Current and Battery Regulation Voltage - ILIM/VSET
        2. 8.2.2.2 Fast Charge Current- ISET
        3. 8.2.2.3 Recommended Passive Components
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.3 Recommended Passive Components

Low ESR ceramic capacitors, such as X7R or X5R, are preferred for input decoupling capacitors and should be placed as close as possible to the supply and ground pins of the IC. Due to voltage derating of the capacitors, it is recommended that 25V rated capacitors are used for the IN and SYS pins, which normally operate at 5V. After derating, the minimum capacitance must be greater than 1µF.

MIN

NOM

MAX

UNIT

CSYS

Capacitance on SYS pin

1

10

100

μF

CBAT

Capacitance on BAT pin

1

1

-

μF

CIN

Capacitance on IN pin (tVIN_PRESENT > 25ms)

1

μF