SLUSFL6C November   2024  – June 2025 TPSM82866C

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 7.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 7.3.5 Enable and Soft-Start Ramp
      6. 7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Start-Up Output Voltage and I2C Target Address Selection (VSET)
      3. 7.4.3 Select Output Voltage Registers (VID)
      4. 7.4.4 Output Discharge
      5. 7.4.5 Power Good (PG)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-Mode, Fast-Mode, and Fast-Mode Plus Protocol
      3. 7.5.3 HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.5 Power Good (PG)

The TPSM8286xExx module versions are device options with a VSET/PG pin, instead of the VSET/VID pin, shown in Section 4.

After the enable delay (tDelay), the device starts to compare the output voltage with the configured value inside the VOUT Register 1. Table 7-2 shows the logic level of the VSET/PG pin. The pin is driven high to the input voltage for a logic high. The pin is pulled to GND by the external resistor for a logic low.

For the VSET/PG option devices, be aware of the following:

  • The source current of the VSET/PG pin is up to 1mA.
  • VOUT Register 2 is disabled.
  • When the device is in shutdown, the shutdown current is increased because of the leakage current through the external resistor R4, when the VSET/PG pin is high.

The VSET/PG has a 34µs deglitch time, before the signal goes high or low, during normal operation. See Figure 7-3. For start-up, the VSET/PG has a delay time of 200μs after the output voltage reaches the nominal voltage.

Table 7-2 VSET/PG Pin Logic
DEVICE CONDITIONS LOGIC STATUS
HIGH LOW
Enable 0.91 × VOUT_NOM ≤ VVOUT ≤ 1.11 × VOUT_NOM √
VVOUT < 0.91 × VOUT_NOM or VVOUT > 1.11 × VOUT_NOM √
Shutdown EN = low √
Thermal shutdown TJ > TJSD √
UVLO 1.8V < VIN < VUVLO √
Power supply removal VIN < 1.8V undefined
TPSM82866C VSET/PG Transient and Delay BehaviorFigure 7-3 VSET/PG Transient and Delay Behavior