SLUUBT5C November 2018 – June 2021 BQ40Z80
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | Configuration | Temperature Enable | H1 | 0x0 | 0x1F | 0x6 | Hex |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | RSVD | RSVD | TS4 | TS3 | TS2 | TS1 | TSint |
| RSVD (Bits 7–5): Reserved. Do not use. | ||
| TS4 (Bit 4): Enable TS4 | ||
| 1 = | Enables TS4 (default) | |
| 0 = | Disables TS4 | |
| TS3 (Bit 3): Enable TS3 | ||
| 1 = | Enables TS3 (default) | |
| 0 = | Disables TS3 | |
| TS2 (Bit 2): Enable TS2 | ||
| 1 = | Enables TS2 (default) | |
| 0 = | Disables TS2 | |
| TS1 (Bit 1): Enable TS1 | ||
| 1 = | Enables TS1 (default) | |
| 0 = | Disables TS1 | |
| TSint (Bit 0): Enable internal TS | ||
| 1 = | Enables internal TS | |
| 0 = | Disables internal TS (default) | |