SLUUC97B June   2020  – January 2025 UCC21222-Q1 , UCC21330-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Failure Mode Distribution (FMD)

The failure mode distribution estimation for UCC21222-Q1 and UCC21330-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
OUTA stuck low 15
OUTB stuck low 15
OUTA and OUTB stuck low 2
OUTA stuck high 10
OUTB stuck high 10
DT out of specified range 3
OUTA unknown or not in specified range 9
OUTB unknown or not in specified range 9
OUTA or OUTB stuck low 1
OUTA or OUTB stuck high 1
OUTA and OUTB unknown or not in specified range
OUTA or OUTB unknown or not in specified range
15
No effect or distribution less than 1% 10

The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to IEC 61800-5-2:2016 if the following requirements are fulfilled:

  1. The signal isolation component is OVC III according to IEC 61800-5-1. If a SELV/PELV power supply is used, pollution degree 2/OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
  2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.