SLUUD60B October   2024  – May 2025 UCG28826

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 Additional Images
      1. 2.1.1 Using the EVM on a Load with USB-C PD Communication
      2. 2.1.2 Using the EVM on a Load Without USB-C PD Communication
  9. 3Implementation Results
    1. 3.1 Electrical Performance Specifications
    2. 3.2 Test Setup
      1. 3.2.1 Test Setup Requirements
      2. 3.2.2 Test Setup Diagram
      3. 3.2.3 Test Points
    3. 3.3 Performance Data and Typical Characteristic Curves
      1. 3.3.1  Efficiency Result of 4-Point Average on 20VOUT
      2. 3.3.2  Efficiency Result of 4-Point Average at 15VOUT
      3. 3.3.3  Efficiency Result of 4-Point Average at 9VOUT
      4. 3.3.4  Efficiency Result of 4-Point Average at 5VOUT
      5. 3.3.5  Efficiency Typical Results
      6. 3.3.6  Output Characteristics
      7. 3.3.7  Key Switching Waveforms
      8. 3.3.8  Switching Frequency vs Load
      9. 3.3.9  Output Ripple Voltage
      10. 3.3.10 Load Transient Response
      11. 3.3.11 Line Transient Response
      12. 3.3.12 Surge Test
      13. 3.3.13 Short Term Overload Operation
      14. 3.3.14 CCM operation
      15. 3.3.15 EN55022 Class B Conducted EMI Test Result
      16. 3.3.16 Thermal Images at Full Load (20V and 3.25A)
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Transformer Details
      1. 4.3.1 RLTI-1464 (RENCO)
    4. 4.4 Bill of Materials
  11. 5Appendix - Efficiency
    1. 5.1 Efficiency Result of 4-Point Average on 20VOUT
    2. 5.2 Efficiency Result of 4-Point Average on 15VOUT
    3. 5.3 Efficiency Result of 4-Point Average on 9VOUT
    4. 5.4 Efficiency Result of 4-Point Average on 5VOUT
    5. 5.5 Efficiency Typical Results
  12. 6Additional Information
    1.     Trademarks
  13. 7Revision History

3.2.3 Test Points

Table 3-2 Input/Output Terminals and Test Point Functions
Terminals and TEST POINTS NAME DESCRIPTION
J1 J1 Terminal J1 USB-C
J2-L J2 Terminal L AC voltage input - Line
J2-N N AC voltage input - Neutral
TPL Input test points TPL1 AC input monitor - Line
TPN Input test points TPN1 AC input monitor - Neutral
TP1 Bulk

voltage

 VBULK

Bulk voltage measurement point
TP5

, TP9

Power / Primary GND

 PGND Ground

TP6

Drain

VSW

Switch node voltage

TP8

Feedback

FB

Feedback pin voltage

TP2

Source

SRC

Source of SR FET

TP3

Drain

VOUT

Drain of SR FET

TP7

SR Gate

GATE

SR FET gate voltage pin

TP10

Output bus voltage

VBUS

Bus voltage at output side

TP11

Output return line

RTN

Return line atoutput side