SLVAE87B December   2020  – June 2025 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD Outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP or BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Reclocking
      1. 9.3.1 Design Summary
  13. 10Multidrop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Summary
  20. 17References
  21. 18Revision History

13.1 Ground Planes

Establish a clean grounding scheme to make sure of best performance of the device. There are three ground pins (AVSS, DVSS, CVSS) for the internal power supplies of the device and one ground reference (REFHM) for the precision reference. There are noisy grounds and quiet grounds that are separated in the layout initially and joint together in a lower PCB layer. The external components (for example, bypass capacitors) are tied to the proper grounding group if possible to keep the separation of noisy and quiet grounds apart.

  • AVSS ground:
    • Bypass capacitor for these pins: BAT, VC0, CB0, LDOIN, TSREF
    • Package lower pad
  • DVSS ground:
    • Bypass capacitor for DVDD
    • GPIO filter capacitor (if used). This can also connect to AVSS ground plane if needed
  • CVSS ground:
    • Bypass capacitor for CVDD
    • The bypass capacitors for COMHP/N and COMLP/N
  • REFHM ground:
    • Bypass capacitor for REFHP
    • If possible, then separate out REFHM from AVSS on the signal connection layer and reconnect REFHM to the AVSS ground plane on a lower layer

Even on a PCB layer that is mainly for signal routing, a best practice to have as small an island of ground pour as possible to provide a low impedance ground, rather than simply by down the ground trace to an lower ground plane.

Grounding Layout Consideration
Note: The vias shown above are on all four layers. Layer 4 is not shown but includes any traces needed for bottom layer components and a solid ground plane otherwise.
Figure 13-1 Grounding Layout Consideration

There is a strong recommendation to have a minimum of four layers in the PCB, with one fully dedicated as an unbroken VSS plane (except thermal reliefs). Avoid placing tracks on this layer to maintain the unbroken integrity of the plane structure.

If multiple devices are placed on the same PCB, then each device has a ground plane with proper layout clearance.

Separate Ground Plane per Device on the Same PCB Figure 13-2 Separate Ground Plane per Device on the Same PCB