SLVAEW7 September   2020 ADC12DJ5200RF , LMK00304 , LMK04828 , LMX2594 , TPS62912 , TPS62913

 

  1.   Trademarks
  2. 1Introduction and System Description
    1. 1.1 Introduction
      1. 1.1.1 ADC12DJ5200 Noise and Ripple Requirements
      2. 1.1.2 Power Supply Requirements for Wideband RF PLL and Clocks
      3. 1.1.3 TPS62913 Low-Noise and Low-Ripple Buck Converter
    2. 1.2 Block Diagram
    3. 1.3 Design Considerations
  3. 2Tests and Results
    1. 2.1 Test Methodology
    2. 2.2 Test Conditions
    3. 2.3 Test Results
  4. 3Conclusion
  5. 4References
  6. 5Appendix

1.3 Design Considerations

The ADC12DJ5200 is a high performance multi giga sample per second (GSPS) ADC and is sensitive to noise and spurious contents that result from high current in the switching elements, output capacitor ESL, and the magnetics involved when using a standard DC/DC converter. Utilizing the TPS62913 low-ripple, low-noise converter enables a significant reduction in noise and ripple without using a post-regulation LDO through the converters' unique low-ripple and low-noise design features.

The converter’s analog and clock inputs often get most of the scrutiny when it comes to addressing low noise on their inputs. Keep in mind that power supplies are inputs too. Because we think of them as DC biasing circuits we often don’t think of them as relating to RF performance. However, this is not true. When designing power supply domains for any high-speed converter, here are some useful tips in maximizing power supply noise immunity:

  • Decouple all power supply rails and bus voltages as they come onto the system board and near/at the ADC itself.
  • Remember that approximately 20 dB/decade noise suppression is gained for each additional filtering stage.
  • Decouple for both high and low frequencies, which might require multiple capacitor values.
  • Series ferrite beads are commonly used at the power entry point. just before the decoupling capacitor to ground. This should be done for each individual supply voltage coming in on the system board whether it comes from an LDO or switcher regulator.
  • For added capacitance, use tightly stacked power and ground plane pairs (≤4 mil spacing) this adds inherent high-frequency (>500MHz) decoupling to the PCB design.
  • Keep supplies away from sensitive analog circuitry such as the front-end stage of the ADC and clocking circuits if possible.
  • Some components could be located on the opposite side of the PCB for added isolation.
  • Follow the IC manufacture recommendations; if they are not directly stated in the application note or data sheet, then study the evaluation board. These are great vehicles to learn from.

Applying these points above can help provide a solid power supply design yielding datasheet performance in many applications.