SLVS337E March   2001  – January 2025 TPS792

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Active Discharge (New Chip)
      4. 6.3.4 Foldback Current Limit
      5. 6.3.5 Thermal Protection
      6. 6.3.6 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Operation
      2. 7.1.2 Exiting Dropout
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitor Recommendations
        2. 7.2.2.2 Input and Output Capacitor Requirements
        3. 7.2.2.3 Noise Reduction and Feed-Forward Capacitor Requirements
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Power Dissipation and Junction Temperature
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Revision History

Changes from Revision D (December 2024) to Revision E (January 2025)

  • Added New Chip to Layout Example (DBV 5-Pin Package) figure captionGo

Changes from Revision C (December 2024) to Revision D (December 2024)

  • Added Layout Example (DBV 5-Pin Package) figureGo

Changes from Revision B (May 2002) to Revision C (December 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed entire document to align with current family formatGo
  • Added M3 devices to documentGo
  • Added NC/NR pinGo
  • Updated Pin Description table to include new chip and legacy chip descriptionsGo
  • Added suggestion to look at TPS7A20 for lower noise performanceGo