SLVSB16E November   2011  – December 2015 TPS43340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Inputs
      2. 7.3.2 Linear Regulator (LREG1)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GPULL) and Reverse Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Synchronous Buck Converter Buck3
        1. 7.3.6.1 Soft Start and Foldback Functions
        2. 7.3.6.2 Current-Mode Control and Current-Limit Protection
        3. 7.3.6.3 Operation in Dropout and Undervoltage Protection
        4. 7.3.6.4 Slew Rate Control (SLEW)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Setting the Operating Frequency
        2. 7.4.1.2 Feedback Inputs
        3. 7.4.1.3 Soft-Start Inputs
        4. 7.4.1.4 Current-Mode Operation
        5. 7.4.1.5 Current Sensing and Current Limit With Foldback
        6. 7.4.1.6 Slope Compensation
        7. 7.4.1.7 Reset Outputs and Filter Delays
        8. 7.4.1.8 Light-Load PFM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High- and Low-Side Power NMOS Selection for the Buck Converters
        2. 8.2.2.2 Buck1 Component Selection
        3. 8.2.2.3 Buck2 Component Selection
        4. 8.2.2.4 Buck3 Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
      1. 10.3.1 Power Dissipation of Buck1 and Buck2 (VOUT1 and VOUT2)
      2. 10.3.2 Power Dissipation of Buck Converter Buck3 (VOUT3)
        1. 10.3.2.1 High-Side Switch
        2. 10.3.2.2 Low-Side Switch
        3. 10.3.2.3 Linear Regulator (LREG1)
        4. 10.3.2.4 IC Power Consumption
    4. 10.4 Thermal Considerations
      1. 10.4.1 Phase Configuration
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply inputs Input voltage VIN –0.3 60 V
Buck controller
Buck1 and Buck2		 Enable inputs EN1, EN2 –0.3 60 V
Bootstrap supplies BOOT1, BOOT2 –0.3 68 V
Bootstrap supplies BOOT1-PH1, BOOT2-PH2, BOOT3-PH3 –0.3 8.8 V
Phase inputs PH1, PH2 –1 60 V
PH1, PH2 (for 100 ns) –2 V
Feedback inputs VSENSE1, VSENSE2 –0.3 13 V
Error-amplifier outputs COMP1, COMP2 –0.3 13 V
Peak output currents from external MOSFET driver GU1,GU2, GL1,GL2 1 A
External MOSFET driver GL1-PGND1,GL2-PGND2 –0.3 8.8 V
GU1-PH1,GU2-PH2 –0.3 8.8
Current-sense voltage S1, S2, S3, S4 –0.3 13 V
Absolute differential voltage |S1 – S2|, |S3 – S4| 2 V
Soft start SS1, SS2 –0.3 13 V
Power-good outputs RST1, RST2 –0.3 13 V
Switching-frequency oscillator RT –0.3 13 V
External input clock SYNC –0.3 13 V
External input supply for gate drive EXTSUP –0.3 13 V
Buck converter
Buck3		 Input supply VSUP –0.3 13 V
Slew-rate setting SLEW –0.3 13
Enable input EN3 –0.3 13
Bootstrap supply BOOT3 –1 20
Phase inputs PH3 –1 13
PH3 (for 100 ns) –2
Feedback input VSENSE3 –0.3 13
Soft start SS3 –0.3 13
Power-good output RST3 –0.3 13
Error-amplifier output COMP3 –0.3 13
Linear regulator
LREG1 		Input voltage VLR1 –0.3 60 V
Output voltage LREG1 –0.3 7
Enable input EN4 –0.3 60
Power-good output RST4 –0.3 8.8
Feedback inputs VSENSE4 –0.3 13
GPULL, Rdelay, VREG, VIN2SENSE PMOS driver GPULL –0.3 60 V
Zener clamp current GPULL 0.2 mA
Internal regulator VREG –0.3 8.8 V
Reset delay Rdelay –0.3 8.8 V
Supply sense input VIN2SENSE –0.3 60 V
Temperature Junction temperature: TJ –40 150 °C
Operating temperature: TA –40 125
Storage temperature: TSTG –55 165
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins except VLR1 ±2000 V
VLR1 ±1000
Charged device model (CDM), per AEC Q100-011 Corner pins (1, 12, 13, 24, 25, 36, 37, and 48) ±750
Other pins ±500
Machine model (MM) All pins except RSTx ±200
RSTx ±100
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply inputs Input voltage VIN 4 40 V
Input voltage for Buck 2 VIN2SENSE 4 40 V
Buck controller
Buck1 and Buck2		 Enable inputs EN1, EN2 0 40 V
Bootstrap inputs BOOT1, BOOT2 4 48 V
Phase inputs PH1, PH2 –0.6 40 V
PH1, PH2 (for 50 ns) –2 V
Feedback inputs VSENSE1, VSENSE2 0 6 V
Error-amplifier outputs COMP1, COMP2 0 6 V
Peak output currents from external MOSFET driver GU1,GU2, GL1,GL2 0.75 A
Current-sense voltage S1, S2, S3, S4 0 11 V
Soft start SS1, SS2 0 6 V
Power-good outputs RST1, RST2 0 11 V
Switching-frequency setting RT 0 1.2 V
External input clock SYNC 0 9 V
External input supply for gate drive EXTSUP 0 9 V
Buck converter
Buck3		 Input supply VSUP 4 10 V
Slew-rate setting SLEW 0 VREG
Enable input EN3 0 6
Boot inputs BOOT3 0 18
Phase inputs PH3 –1 11
PH3 (for 50 ns) –2
Feedback input VSENSE3 0 6
Soft start SS3 0 6
Power-good output RST3 0 11
Error-amplifier output COMP3 0 6
Linear regulator
LREG1 		Input voltage VLR1 4 40 V
Output voltage LREG1 0.8 5.25
Enable input EN4 0 40
Power-good output RST4 0 5.25
Feedback inputs VSENSE4 0 6
PMOS driver PMOS driver GPULL 4 40 V
Internal regulator VREG 0 6
Temperature ratings Operating temperature, TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS43340-Q1 UNIT
PHP (HTQFP)
48 PINS
RθJA Junction-to-ambient thermal resistance 26.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.2 °C/W
RθJB Junction-to-board thermal resistance 7.2 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 7.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

VIN = VLR1 = 8 V to 18 V, VSUP = 4 V to 10 V, VIN2SENSE = 4 V to 40 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage required for device on initial start-up 6.5 40 V
Operating range after initial start-up 4 V
VIN UV Undervoltage lockout VIN falling. After a reset, initial start-up conditions may apply.(1) 3.5 3.6 3.8 V
VIN rising. After a reset, initial start-up conditions may apply.(1) 3.8 4 V
VLR1 Device operating range for linear regulator 4 40 V
IQ Quiescent current TA = 25°C EN1 = 1, LPM; EN2,3,4 = 0 30 40 µA
EN2 = 1, LPM; EN1,3,4 = 0 30 40
EN4 = 1, LPM; EN1,2,3 = 0 48 60
EN1,2 = 1, LPM; EN3,4 = 0 35 45
EN3,4 = 1, EN1,2 = 0 4 4.5 mA
TA = 125°C EN1 = 1, LPM; EN2,3,4 = 0 40 50 µA
EN2 = 1, LPM; EN1,3,4 = 0 40 50
EN4 = 1, LPM; EN1,2,3 = 0 52 60
EN1,2 = 1, LPM; EN3,4 = 0 40 45
EN3,4 = 1, EN1,2 = 0 5 mA
IVIN Quiescent current TA = 25°C VIN = 13 V, Buck1: CCM, Buck2: off, or
VIN = 13 V, Buck2: CCM, Buck1: off, or
VIN = 13 V, Buck1 and Buck2: CCM		 5 mA
TA = 125°C Normal operation, SYNC = 5 V 5 mA
VIN = 13 V, Buck1: CCM, Buck2: off 5
VIN = 13 V, Buck2: CCM, Buck1: off 5
VIN = 13 V, Buck1, 2: CCM 7
IVIN-SD Shutdown current at TA = 25°C EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V 5 10 µA
IVIN-SD Shutdown current at TA = 125°C EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V 20 µA
IVLRI-SD Shutdown current at TA = 125°C EN1,2,3,4 = 0: off, VIN = VLR1 = 13 V 5 µA
INTERNAL SUPPLY VREG
VREG Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High 5.5. 5.8 6.1 V
Load regulation EXTSUP = 0 V, SYNC = High IVREG = 0 mA to 100 mA 0.2% 1%
VREG-EXTSUP Internal regulated supply EXTSUP = 8.5 V 7.2. 7.5 7.8 V
Load regulation EXTSUP = 8.5 V to 13 V, IVREG = 0 mA to 125 mA, SYNC = High 0.2% 1%
VEXTSUP-VREG EXTSUP switch-over voltage IVREG = 0 mA to 100 mA, EXTSUP ramping positive 4.4 4.6 4.8 V
VEXTSUP-HYS EXTSUP switch-over hysteresis 150 250 mV
IREG-LIM Current limit on VREG EXTSUP = 0 V normal mode as well as LPM 100 400 mA
IREG-EXTSUP-LIM Current limit on VREG when using EXTSUP IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High 125 400 mA
INPUT VOLTAGE VIN - OVERVOLTAGE LOCK OUT AND REVERSE POLARITY PROTECTION
VOVLO Overvoltage shutdown VIN rising 45 46 47 V
VIN falling 43 44 45 V
OVLOHys Hysteresis 1 2 3 V
OVLOfilter Filter time 5 µs
VGD Clamping voltage of ext. FET VIN - GPULL 17 V
RGPULL Internal resistance to GND 500 kΩ
BUCK CONTROLLERS
VOUT1, VOUT2 Adjustable output voltage range 0.9 11 V
VREF Internal reference voltage and tolerance in normal mode Measure VSENSEx pin 0.792 0.8 0.808 V
–1% 1%
VREF, LPM Internal reference voltage and tolerance in low-power mode Measure VSENSEx pin 0.784 0.8 0.816 V
–2% 2%
VSENSE VSENSE for forward-current limit in CCM VSENSEx = 0.75 V, duty cycles < 10% 60 75 90 mV
VSENSE for reverse-current limit in CCM VSENSEx = 1 V –65 –37.5 –23 mV
VI-Foldback VSENSE for output short VSENSEx = 0 V (foldback) 17 43.8 48 mV
tdead Shoot through delay, blanking time 20 ns
DCNRM High-side minimum on-time 100 ns
Maximum duty cycle (digitally controlled) 98.75%
DCLPM Duty cycle LPM 80%
ILPM_Entry LPM entry threshold load current as fraction of maximum set load current 1%
VLPM_Exit LPM exit threshold load current as fraction of maximum set load current 10%
HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLERS
IGUx_peak Gate driver peak current 0.6 A
rDS(on) Source and sink driver VREG = 5.8 V, IGUx current = 200 mA 5 Ω
LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLERS
IGLx_peak Gate driver peak current 0.6 A
rDS(on) Source and sink driver VREG = 5.8V, IGLx current = 200 mA 5 Ω
INTERNAL OSCILLATOR (RT)
fSW Buck switching frequency RT pin: GND 360 400 440 kHz
fSW Buck switching frequency RT pin: 60 kΩ external resistor 360 400 440 kHz
fSW-adj Buck adjustable range with external resistor RT pin: external resistor 150 600 kHz
fsync Buck synch. range External clock input on SYNC 150 600 kHz
VRT Oscillator reference voltage 1.2 V
tSW-Prop dly SYNC rising edge to PH rising edge delay 0 20 40 ns
tSW-Trans-delay Last SYNC rising edge to return to resistor mode if CLK is not present on SYNC pin 20 µs
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BUCK CONVERTER
IPULLUP_VSENSEx Pullup current at VSENSEx pins VSENSEx = 0 V 50 100 200 nA
gm Forward transconductance COMP1, COMP2 = 0.8 V; source/sink = 5 µA, Test in feedback loop 0.7 0.9 1.35 mS
EXTERNAL CLOCK AND ENABLE INPUTS: SYNC. EN1, EN2, EN3, EN4
VIH Higher threshold VIN = 13 V 1.7 V
VIL Lower threshold VIN = 13 V 0.7 V
RIH Pulldown resistance VSYNC = 5 V 500 kΩ
IIL_ENx Pullup current VENx = 0V 0.5 2 µA
tdeglitch Deglitch time, ENx 2 16 µs
LINEAR REGULATOR LREG1
VLREG1 Regulated output range IL = 10 µA to 300 mA 0.8 5.25 V
VREF Internal reference voltage tolerance Referred to 0.8-V VREF, measured at VSENSE4 –2.5% 2.5%
Vline-reg Line regulation VIN = VLR1: 6 V to 28 V, IOUT 4 = 10 mA, ∆VOUT, VOUT = 5 V 15 mV
∆VOUT, VOUT = 3.3 V 15
∆VOUT, VOUT = 1.5 V 15
Vload-reg Load regulation IOUT4 = 10 mA to 300 mA, VIN = 14 V ∆VOUT, VOUT = 5 V 10 mV
∆VOUT, VOUT = 3.3 V 10
∆VOUT, VOUT = 1.5 V 10
VDropout Drop out voltage VIN = VLR1 = 4 V: IOUT = 250 mA 500 mV
VIN = 9 V, VLR1 = 4 V: IOUT = 150 mA 300
IOUT4 Output current VOUT in regulation 0.01 300 mA
ILREG1-CL Output current limit VOUT = 0 V 400 1000 mA
dVLREG1 / dt Output soft start slew rate 5 V/ms
PSRR Power supply ripple rejection Vripple = 0.5 VPP, IOUT = 300 mA Freq = 100 Hz 60 dB
Freq = 150 kHz 25
VTH-CP ONp Charge-pump turnoff voltage, VIN rising 9.4 V
Hysteresis 0.18 V
ITH-CP-OFF Low-load current-detection threshold IOUT4 falling 2 mA
Low-load current-detection hysteresis 4 mA
SOFT START SSX
ISSx Soft-start source current SSx = 0 V 0.75 1 1.25 µA
RESET RSTx
RSTpullup RST1 to S2, RST2 to S4, RST4 to LREG1 internal pullups 50 kΩ
RSTxth1 Reset threshold VSENSEx falling –5 –7 –9.5 %VREF
RSTxhys Hysteresis 2 %VREF
RSTxdrop Voltage drop IRSTx = 5 mA 450 mV
IRSTx = 1 mA 100 mV
RSTxleak Leakage VS2 = VS4 = VRSTx = 13 V, RST4 = 8 V 1 µA
tdeglitch Power-good deglitch time 2 16 µs
tdelay Reset release delay External capacitor = 1 nF 1 ms
tdelay_fix Fixed reset delay No external capacitor, Rdelay pin open 20 50 µs
IOH Activate current source (current to charge external capacitor) Current to charge external capacitor 30 40 50 µA
IIL Activate current sink (current to discharge external capacitor) Current to discharge external capacitor 30 40 50 µA
SYNCHRONOUS BUCK CONVERTER BUCK3
VSUP Buck3 supply voltage 4 10 V
VSUP_UV Buck3 undervoltage lockout VSUP falling 3.6 3.7 3.8 V
VSUP rising 3.7 3.8 3.9 V
rDS(on) High-side switch VSUP = 9 V, VBoot3 –PH3 = 5.8 V 0.14 0.28 Ω
Low-side switch VSUP = 9 V, VVREG-PGND3 = 5.8 V 0.15 0.28 Ω
IHS-Limit High-side switch 2.5 A
ILS-Limit Low-side switch, current into PH3 2.38 A
VSUPLkg VSUP leakage current VSUP = 10 V for high side, EN3 = Low. TJ = 100°C 1 µA
IFB3 Current foldback VSENSE3 = 0 V 1.9 A
fSW-adj Buck3 switching frequency range with external resistor Using external resistor on RT/CLK 150 600 kHz
VSense Feedback voltage Internal ref = 0.8 V –1.5% 1.5%
fSW-f-back 2-times - frequency foldback exit threshold, VSENSE3 rising 0.65 V
2-times - frequency foldback entry threshold, VSENSE3 falling 0.6 V
Gm3 Current loop transconductance ΔIpeakPH3 / ΔVCOMP3 5.4 S
DC3 Minimum duty cycle fSW = 400 kHz, SLEW = LOW or OPEN 10%
Maximum duty cycle In dropout operation 98.75%
TOT-BUCK3 Overtemperature sensor threshold, leads to Buck3 FET deactivation 170 °C
TOT-BUCK3-HYS Overtemperature sensor hysteresis 15 °C
THERMAL SHUTDOWN
Tshutdown Junction temperature shutdown threshold 150 170 °C
Thys Junction temperature hysteresis 15 °C
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V

6.6 Typical Characteristics

TPS43340-Q1 g_buck2_lvsb16.gif
VOUT = 3.3 V VIN = 5 V
Figure 1. Buck2 Efficiency versus Output Current Continuous Mode
TPS43340-Q1 g_iq_ivin_SLVSB16.gif
Figure 3. VIN Shutdown Current vs VIN
TPS43340-Q1 g_buck_load_step_low_power_entry_lvsa82_1428721.gif
VIN = 12 V VOUTx = 5 V RSENSE = 10 mΩ
Inductor = 4.7 µH Switching Frequency = 400 kHz
Figure 5. Buck1 and Buck2 Load Step: Low-Power-Mode Entry (0.09 mA to 4 A at 2.5 A/µs)
TPS43340-Q1 g_inductor_current_buck_lvsb16.gif
VIN = 12 V VOUTx = 5 V RSENSE = 10 mΩ
Inductor = 4.7 µH Switching Frequency = 400 kHz
Figure 7. Inductor Currents (Buck1 and Buck2)
TPS43340-Q1 g_foldback_current_SLVSB16.gif
Figure 9. Foldback Current Limit (Buck3)
TPS43340-Q1 g_vgpull_SLVSB16.gif
Figure 11. GPULL Voltage vs VIN
TPS43340-Q1 g_slope_combine_SLVSB16.gif
VSUP = 4, 5, OR 6 V Inductor = 10 µH VSENSE3 = 0.75 V
Switching Frequency = 400 kHz
Figure 13. Buck3 Maximum Peak Inductor Current vs Duty Cycle
TPS43340-Q1 g_buck3_lvsb16.gif
VIN = 14 V VOUT = 3.3 V VSUP = 4 V
Figure 2. Buck3 Efficiency vs Output Current, 400 kHz 25°C
TPS43340-Q1 g_reg_fbx_volt_temp_buck_SLVSB16.gif
Figure 4. Regulated VSENSEx Voltage vs Temperature (Buck1 and Buck2)
TPS43340-Q1 g_buck_load_step_low_power_exit_lvsb16.gif
VIN = 12 V VOUTx = 5 V RSENSE = 10 mΩ
Inductor = 4.7 µH Switching Frequency = 400 kHz
Figure 6. Buck1 AND Buck2 Load Step: Low-Power-Mode Exit (0.09 mA to 4 A AT 2.5 A/µs)
TPS43340-Q1 g_buck_fold_SLVSB16.gif
Figure 8. Foldback Current Limit (Buck1 and Buck2)
TPS43340-Q1 g_current_sense_pins_input_current_buck_lvsb16.gif
Figure 10. Current Sense Pins Input Current (Buck1 and Buck2)
TPS43340-Q1 g_current_limit_duty_cycle_buck_SLVSB16.gif
Figure 12. Current Limit vs Duty Cycle (Buck1 and Buck2)