SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)

Table 7-138 SYSREF Calibration Registers
ADDRESSRESETACRONYMREGISTER NAMESECTION
0x2B00x00SRC_ENSYSREF Calibration Enable RegisterGUID-8933E19F-1BD0-469C-8C5E-4A82770806B7.html#SLVSDR23876
0x2B10x05SRC_CFGSYSREF Calibration Configuration RegisterGUID-8933E19F-1BD0-469C-8C5E-4A82770806B7.html#SLVSDR23234
0x2B2-0x2B4UndefinedSRC_STATUSSYSREF Calibration StatusGUID-8933E19F-1BD0-469C-8C5E-4A82770806B7.html#SLVSDR25333
0x2B5-0x2B70x00TADDEVCLK Aperture Delay Adjustment RegisterGUID-8933E19F-1BD0-469C-8C5E-4A82770806B7.html#SLVSDR21670
0x2B80x00TAD_RAMPDEVCLK Timing Adjust Ramp Control RegisterGUID-8933E19F-1BD0-469C-8C5E-4A82770806B7.html#SLVSDR27252
0x2B9-0x2BFUndefinedRESERVEDRESERVED—

7.6.2.1 SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]

Figure 7-110 SYSREF Calibration Enable Register (SRC_EN)
76543210
RESERVEDSRC_EN
R/W-0000 000R/W-0
Table 7-139 SRC_EN Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000 000RESERVED
0SRC_ENR/W00: SYSREF calibration disabled; use the TAD register to manually control the TAD[16:0] output and adjust the DEVCLK delay (default)
1: SYSREF calibration enabled; the DEVCLK delay is automatically calibrated; the TAD register is ignored

A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Ensure that ADC calibration is not currently running before setting SRC_EN.

7.6.2.2 SYSREF Calibration Configuration Register (address = 0x2B1) [reset = 0x05]

Figure 7-111 SYSREF Calibration Configuration Register (SRC_CFG)
76543210
RESERVEDSRC_AVGSRC_HDUR
R/W-0000R/W-01R/W-01
Table 7-140 SRC_CFG Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000 00RESERVED
3-2SRC_AVGR/W01Specifies the amount of averaging used for SYSREF calibration. Larger values increase calibration time and reduce the variance of the calibrated value.

0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages
1-0SRC_HDURR/W01Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, the calibration fails. Larger values increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values also reduce the variance of the calibrated value.

0: 4 cycles per accumulation, max SYSREF period of 85 DEVCLK cycles
1: 16 cycles per accumulation, max SYSREF period of 1100 DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 5200 DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 21580 DEVCLK cycles

Max duration of SYSREF calibration is bounded by:
TSYSREFCAL (in DEVCLK cycles) = 256 × 19 × 4(SRC_AVG + SRC_HDUR + 2)

7.6.2.3 SYSREF Calibration Status Register (address = 0x2B2 to 0x2B4) [reset = Undefined]

Figure 7-112 SYSREF Calibration Status Register (SRC_STATUS)
2322212019181716
RESERVEDSRC_DONESRC_TAD[16]
RRR
15141312111098
SRC_TAD[15:8]
R
76543210
SRC_TAD[7:0]
R
Table 7-141 SRC_STATUS Field Descriptions
BitFieldTypeResetDescription
23-18RESERVEDRUndefinedRESERVED
17SRC_DONERUndefinedThis bit returns a 1 when SRC_EN = 1 and SYSREF calibration is complete.
16-0SRC_TADRUndefinedThis field returns the value for TAD[16:0] computed by the SYSREF calibration. This field is only valid if SRC_DONE = 1.

7.6.2.4 DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to 0x2B7) [reset = 0x000000]

Figure 7-113 DEVCLK Aperture Delay Adjustment Register (TAD)
2322212019181716
RESERVEDTAD_INV
R/W-0000 000R/W-0
15141312111098
TAD_COARSE
R/W-0000 0000
76543210
TAD_FINE
R/W-0000 0000
Table 7-142 TAD Field Descriptions
BitFieldTypeResetDescription
23-17RESERVEDR/W0000 000RESERVED
16TAD_INVR/W0Invert DEVCLK by setting this bit equal to 1.
15-8TAD_COARSER/W0000 0000This register controls the DEVCLK aperture delay adjustment when SRC_EN = 0. Use this register to manually control the DEVCLK aperture delay when SYSREF calibration is disabled. If ADC calibration or JESD204B is running, TI recommends gradually increasing or decreasing this value (1 code at a time) to avoid clock glitches. See the GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D.html#GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D table for TAD_COARSE resolution.
7-0TAD_FINER/W0000 0000See the GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D.html#GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D table for TAD_FINE resolution.

7.6.2.5 DEVCLK Timing Adjust Ramp Control Register (address = 0x2B8) [reset = 0x00]

Figure 7-114 DEVCLK Timing Adjust Ramp Control Register (TAD_RAMP)
76543210
RESERVEDTAD_RAMP_RATETAD_RAMP_EN
R/W-0000 00R/W-0R/W-0
Table 7-143 TAD_RAMP Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0000 00RESERVED
1TAD_RAMP_RATER/W0Specifies the ramp rate for the TAD[15:8] output when the TAD[15:8] register is written when TAD_RAMP_EN = 1.
0: TAD[15:8] ramps up or down one code per 256 DEVCLK cycles.
1: TAD[15:8] ramps up or down 4 codes per 256 DEVCLK cycles.
0TAD_RAMP_ENR/W0TAD ramp enable. Set this bit if coarse TAD adjustments are desired to ramp up or down instead of changing abruptly.
0: After writing the TAD[15:8] register the aperture delay is updated within 1024 DEVCLK cycles
1: After writing the TAD[15:8] register the aperture delay ramps up or down until the aperture delay matches the TAD[15:8] register