SLVSDR8B April   2018  – February 2023 TPS62147 , TPS62148

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 Power Good (PG)
      3. 9.3.3 MODE
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit And Short Circuit Protection (for TPS62148)
      5. 9.4.5 HICCUP Current Limit And Short Circuit Protection (for TPS62147)
      6. 9.4.6 Soft Start / Tracking (SS/TR)
      7. 9.4.7 Output Discharge Function (TPS62148 only)
      8. 9.4.8 Starting into a Pre-Biased Load
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
      3. 10.1.3 Inductor Selection
      4. 10.1.4 Capacitor Selection
        1. 10.1.4.1 Output Capacitor
        2. 10.1.4.2 Input Capacitor
        3. 10.1.4.3 Soft-Start Capacitor
      5. 10.1.5 Tracking Function
      6. 10.1.6 Output Filter and Loop Stability
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application with Adjustable Output Voltage
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 LED Power Supply
      2. 10.3.2 Powering Multiple Loads
      3. 10.3.3 Voltage Tracking
      4. 10.3.4 Precise Soft-Start Timing
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10.5.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS62147, TPS62148 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity.

See Section 10.5.2 for the recommended layout of the TPS62147, TPS62148, which is designed for common external ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin of TPS62147, TPS62148. Also connect the VOS pin in the shortest way to VOUT at the output capacitor.

Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore the input and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops which conduct an alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB and VOS must be connected with short wires and not nearby high dv/dt signals (for example SW). As they carry information about the output voltage, they must be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1 and R2, must be kept close to the IC and connect directly to those pins and the system ground plane. The same applies to R3 if FB2 is used to scale the output voltage.

The package uses the pins for power dissipation. Thermal vias on the VIN, GND and SW pins help to spread the heat through the pcb.

In case any of the digital inputs EN, FSEL or MODE must be tied to the input supply voltage at VIN, the connection must be made directly at the input capacitor as indicated in the schematics. Please also see the EVM User´s Guide SLVUBE9.