SLVSE46A November 2017 – January 2018 TPS65680
PRODUCTION DATA.
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| LN_CLK (see Figure 1) | ||||||
| f | Input frequency range | PLL active | 40 | 500 | kHz | |
| PLL bypassed | 0 | 15 | MHz | |||
| tw | High-level pulse width | PLL active | 25 | ns | ||
| tw(1) | Low-level pulse width | PLL active | 25 | ns | ||
| tr(1) | Rise time | PLL active | 25 | ns | ||
| PLL bypassed | (1/2f) - 27 | |||||
| tf(1) | Fall time | PLL active | 25 | ns | ||
| PLL bypassed | (1/2f) - 27 | |||||
| Duty cycle (tw(2) × f) | 40 | 60 | % | |||
| LS_START (see Figure 2) | ||||||
| tw(3) | High-level pulse width | 15 | 500 | µs | ||
| tsu | Setup time (PLL bypass mode only) | 50 | 450 | ns | ||
| th | Hold time (PLL bypass mode only) | 50 | ns | |||
| t21 | Delay between rising edge of LN_CTRL & EN_DLY and LS_START. | 72 | µs | |||
| I2C-INTERFACE (see Figure 3) | ||||||
| fSCL | SCL clock frequency | Standard-mode | 100 | kHz | ||
| Fast-mode | 400 | |||||
| Fast-mode Plus | 1000 | |||||
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated | Standard-mode | 4.0 | µs | ||
| Fast-mode | 0.6 | |||||
| Fast-mode Plus | 0.26 | |||||
| tLOW | LOW period of the SCL clock | Standard-mode | 4.7 | µs | ||
| Fast-mode | 1.3 | |||||
| Fast-mode Plus | 0.5 | |||||
| tHIGH | HIGH period of the SCL clock | Standard-mode | 4.0 | µs | ||
| Fast-mode | 0.6 | |||||
| Fast-mode Plus | 0.26 | |||||
| tSU;STA | Set-up time for a repeated START condition | Standard-mode | 4.7 | µs | ||
| Fast-mode | 0.6 | |||||
| Fast-mode Plus | 0.26 | |||||
| tHD;DAT | Data hold time | Standard-mode | 0.05 | µs | ||
| Fast-mode | 0.05 | |||||
| Fast-mode Plus | 0.05 | |||||
| tSU;DAT | Data set-up time | Standard-mode | 250 | ns | ||
| Fast-mode | 100 | |||||
| Fast-mode Plus | 50 | |||||
| tr | Rise time of both SDA and SCL signals | Standard-mode | 1000 | ns | ||
| Fast-mode | 20 + 0.1 Cb(1) | 300 | ||||
| Fast-mode Plus | 120 | |||||
| tf | Fall time of both SDA and SCL signals | Standard-mode | 300 | ns | ||
| Fast-mode | 20 + 0.1 Cb(1) | 300 | ||||
| Fast-mode Plus | 120 | |||||
| tSP | Pulse width of spikes that are suppressed by the input filter | Standard-mode | 0 | 50 | ns | |
| Fast-mode | 0 | 50 | ||||
| Fast-mode Plus | 0 | 50 | ||||
| tSU;STO | Set-up time for STOP condition | Standard-mode | 4.0 | µs | ||
| Fast-mode | 0.6 | |||||
| Fast-mode Plus | 0.26 | |||||
| tBUF | Bus Free Time Between Stop and Start Condition | Standard-mode | 4.7 | µs | ||
| Fast-mode | 1.3 | |||||
| Fast-mode Plus | 0.5 | |||||
| Cb | Capacitive load for each bus line | Standard-mode | 400 | pF | ||
| Fast-mode | 400 | |||||
| Fast-mode Plus | 550 | |||||