SLVSFJ1E November   2021  – June 2026 DRV8245-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 HTSSOP (28) Package
      2. 5.1.2 VQFN-HR(16) Package
    2. 5.2 SPI Variant
      1. 5.2.1 HTSSOP (28) Package
      2. 5.2.2 VQFN-HR (16) Package
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1  Power Supply & Initialization
      2. 6.5.2  Logic I/Os
      3. 6.5.3  SPI I/Os
      4. 6.5.4  Configuration Pins - HW Variant Only
      5. 6.5.5  Power FET Parameters
      6. 6.5.6  Switching Parameters with High-Side Recirculation
      7. 6.5.7  Switching Parameters with Low-Side Recirculation
      8. 6.5.8  IPROPI & ITRIP Regulation
      9. 6.5.9  Over Current Protection (OCP)
      10. 6.5.10 Over Temperature Protection (TSD)
      11. 6.5.11 Voltage Monitoring
      12. 6.5.12 Load Monitoring
      13. 6.5.13 Fault Retry Setting
      14. 6.5.14 Transient Thermal Impedance & Current Capability
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Waveforms
      1. 6.7.1 Output switching transients
        1. 6.7.1.1 High-Side Recirculation
        2. 6.7.1.2 Low-Side Recirculation
      2. 6.7.2 Wake-up Transients
        1. 6.7.2.1 HW Variant
        2. 6.7.2.2 SPI Variant
      3. 6.7.3 Fault Reaction Transients
        1. 6.7.3.1 Retry setting
        2. 6.7.3.2 Latch setting
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Independent mode
        4. 7.3.2.4 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Programming - SPI Variant Only
      1. 7.4.1 SPI (Serial Peripheral Interface)
      2. 7.4.2 Standard Frame
      3. 7.4.3 SPI Interface for Multiple Peripherals
        1. 7.4.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.2.3 Independent mode

In this mode, the two half-bridges are configured to be used as two independent half-bridges. The Table 7-7 shows the logic table for bridge control. For load illustration, refer the Load Summary section.

Table 7-7 Control table - Independent mode
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
0 X X X Hi-Z Hi-Z No current SLEEP
1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 0 Refer Off-state diagnostics table No current STANDBY
1 1 0 1 No current STANDBY
1 1 1 1 No current STANDBY
1 0 0 0 L L No current ACTIVE
1 0 0 1 L H(2) ISNS2(1) ACTIVE
1 0 1 0 H(2) L ISNS1(1) ACTIVE
1 0 1 1 H(2) H(2) ISNS1 + ISNS2(1) ACTIVE

For the SPI variant, having independent Hi-Z control of both half-bridges through equivalent bits is possible, S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 7-8 shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control for details on the combined inputs shown in Table 7-8.

Table 7-8 Control table - Independent mode for SPI variant, when SPI_IN is unlocked
nSLEEP DRVOFF1 combined DRVOFF2 combined EN_IN1 combined PH_IN2 combined OUT1 OUT2 IPROPI Device State
0 X X X X Hi-Z Hi-Z No current SLEEP
1 1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 1 0 Refer Off-state diagnostics table No current STANDBY
1 1 1 0 1 No current STANDBY
1 1 1 1 1 No current STANDBY
1 1 0 X 0 Hi-Z L No current ACTIVE
1 1 0 X 1 Hi-Z H(2) ISNS2(1) ACTIVE
1 0 1 0 X L Hi-Z No current ACTIVE
1 0 1 1 X H(2) Hi-Z ISNS1(1) ACTIVE
1 0 0 0 0 L L No current ACTIVE
1 0 0 0 1 L H(2) ISNS2(1) ACTIVE
1 0 0 1 0 H(2) L ISNS1(1) ACTIVE
1 0 0 1 1 H(2) H(2) ISNS1 + ISNS2(1) ACTIVE
(1) Current sourcing out of device (VM → OUTx → Load)
(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time

In this mode, the device behavior is as listed below:

  • Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for high-side loads
  • The current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the ITRIP current regulation feature as a combined current regulation, rather than as truly independent.
  • Slew rate configurability is limited for low-side recirculation (low-side loads)
  • Active state open load diagnostics (OLA) is possible only for high-side loads
  • For the HW variant, having independent Hi-Z control of each half-bridge is NOT possible to . Asserting DRVOFF pin high Hi-Zs both the half-bridges.