SLVSHB2A February   2024  – July 2025 DRV8262-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
      1. 5.4.1 Transient Thermal Impedance & Current Capability
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Feature Description
      1. 6.3.1 Spread Spectrum
    4. 6.4  Device Operational Modes
      1. 6.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 6.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 6.5  Current Sensing and Regulation
      1. 6.5.1 Current Sensing and Feedback
      2. 6.5.2 Current Regulation
        1. 6.5.2.1 Mixed Decay
        2. 6.5.2.2 Smart tune Dynamic Decay
      3. 6.5.3 Current Sensing with External Resistor
    6. 6.6  Charge Pump
    7. 6.7  Linear Voltage Regulator
    8. 6.8  VCC Voltage Supply
    9. 6.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 6.10 Protection Circuits
      1. 6.10.1 VM Undervoltage Lockout (UVLO)
      2. 6.10.2 VCP Undervoltage Lockout (CPUV)
      3. 6.10.3 Logic Supply Power on Reset (POR)
      4. 6.10.4 Overcurrent Protection (OCP)
      5. 6.10.5 Thermal Shutdown (OTSD)
      6. 6.10.6 nFAULT Output
      7. 6.10.7 Fault Condition Summary
    11. 6.11 Device Functional Modes
      1. 6.11.1 Sleep Mode
      2. 6.11.2 Operating Mode
      3. 6.11.3 nSLEEP Reset Pulse
      4. 6.11.4 Functional Modes Summary
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Brushed-DC Motors
        1. 7.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 7.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 7.1.1.3 Power Loss Calculations - Single H-bridge
        4. 7.1.1.4 Junction Temperature Estimation
        5. 7.1.1.5 Application Performance Plots
      2. 7.1.2 Driving Stepper Motors
        1. 7.1.2.1 Stepper Driver Typical Application
        2. 7.1.2.2 Power Loss Calculations
        3. 7.1.2.3 Junction Temperature Estimation
      3. 7.1.3 Driving Thermoelectric Coolers (TEC)
    2. 7.2 Power Supply Recommendations
      1. 7.2.1 Bulk Capacitance
      2. 7.2.2 Power Supplies
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Package Thermal Considerations
    1. 8.1 DDW Package
      1. 8.1.1 Thermal Performance
        1. 8.1.1.1 Steady-State Thermal Performance
        2. 8.1.1.2 Transient Thermal Performance
    2. 8.2 PCB Material Recommendation
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.3.1 Layout Guidelines

  • The VM pins is bypassed to PGND pins using low-ESR ceramic bypass capacitors with a recommended value of 0.01µF rated for VM. The capacitors is placed as close to the VM pins as possible with a thick trace or ground plane connection to the device PGND pins.
  • The VM pins must be bypassed to PGND using a bulk capacitor rated for VM. This component can be an electrolytic capacitor.
  • A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1µF rated for VM is recommended. Place this component as close to the pins as possible.
  • A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 1µF rated for 16V is recommended. Place this component as close to the pins as possible.
  • Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 1µF rated for 6.3V is recommended. Place this bypassing capacitor as close to the pin as possible.
  • Bypass the VCC pin to ground with a low-ESR ceramic capacitor. A value of 0.1µF rated for 6.3V is recommended. Place this bypassing capacitor as close to the pin as possible.

  • In general, inductance between the power supply pins and decoupling capacitors must be avoided.

  • The thermal PAD of the DDW package must be connected to system ground.

    • TI recommends to use a big unbroken single ground plane for the whole system / board. The ground plane can be made at bottom PCB layer.
    • To minimize the impedance and inductance, the traces from ground pins are as short and wide as possible, before connecting to bottom layer ground plane through vias.
    • Multiple vias are suggested to reduce the impedance.
    • Try to clear the space around the device as much as possible especially at bottom PCB layer to improve the heat spreading.
    • Single or multiple internal ground planes connected to the thermal PAD also helps spreading the heat and reduce the thermal resistance.