SLVUBX0A July   2021  – January 2022 TPSM8A28 , TPSM8A29

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
  4. 3Getting Started With the TPSM8A29EVM
    1. 3.1 J1 - Input Voltage Supply Connector
    2. 3.2 J4 and J7 - Positive and Negative Output Connectors
    3. 3.3 J2 - Enable Header
    4. 3.4 J5 - Switching Frequency and Operating Mode
    5. 3.5 J6 - Output Voltage Selection Header
  5. 4Test Point Description
    1. 4.1 TP12 - SS/REF_IN
    2. 4.2 TP14 - VCC
  6. 5Test Setup and Results
    1. 5.1 Startup Procedure
    2. 5.2 Efficiency
    3. 5.3 Load Regulation
    4. 5.4 Line Regulation
    5. 5.5 Output Voltage Ripple
    6. 5.6 Startup and Shutdown
    7. 5.7 Load Transient
    8. 5.8 Bode Plot
  7. 6TPSM8A29EVM Schematic
  8. 7TPSM8A29EVM PCB Layers
  9. 8TPSM8A29EVM Bill of Materials
  10. 9Revision History

4.2 TP14 - VCC

TP14 is the VCC test point for the internal LDO. It can be used to monitor the VCC voltage, or it can be used to override the internal LDO of the TPSM8A29 for higher efficiency. Frequently, systems will have an LDO present somewhere in the design which can be used here to reduce the power losses associated with producing a low-noise supply rail with a linear regulator. The internal LDO produces a typical voltage of 4.5 V, so the recommended input range for an external bias on the VCC pin is 4.75 V to 5.3 V. Because of the limited sourcing current capability of the internal LDO, do not connect any external loading to this pin.