SLVUC05A November   2020  – July 2022 TPS25750

 

  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  2. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and Field Notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
      2. 1.3.2 Unique Address Interface Registers
  3. 2Unique Address Interface Register Detailed Descriptions
    1. 2.1  0x03 MODE Register
    2. 2.2  0x0D DEVICE_CAPABILITIES Register
    3. 2.3  0x14 - 0x19 INT_EVENT, INT_MASK, INT_CLEAR Registers
    4. 2.4  0x1A STATUS Register
    5. 2.5  0x26 POWER_PATH_STATUS Register
    6. 2.6  0x29 PORT_CONTROL Register
    7. 2.7  0x2D BOOT_STATUS Register
    8. 2.8  0x30 RX_SOURCE_CAPS Register
    9. 2.9  0x31 RX_SINK_CAPS Register
    10. 2.10 0x32 TX_SOURCE_CAPS Register
    11. 2.11 0x33 TX_SINK_CAPS Register
    12. 2.12 0x34 ACTIVE_CONTRACT_PDO Register
    13. 2.13 0x35 ACTIVE_CONTRACT_RDO Register
    14. 2.14 0x3F POWER_STATUS Register
    15. 2.15 0x40 PD_STATUS Register
    16. 2.16 GPIO Events
    17. 2.17 0x69 TYPEC_STATE Register
    18. 2.18 0x70 SLEEP_CONFIG Register
    19. 2.19 0x72 GPIO_STATUS Register
  4. 34CC Task Detailed Descriptions
    1. 3.1 Overview
    2. 3.2 PD Message Tasks
      1. 3.2.1 'SWSk' - PD PR_Swap to Sink
      2. 3.2.2 'SWSr' - PD PR_Swap to Source
      3. 3.2.3 'SWDF' - PD DR_Swap to DFP
      4. 3.2.4 'SWUF' - PD DR_Swap to UFP
      5. 3.2.5 'GSkC' - PD Get Sink Capabilities
      6. 3.2.6 'GSrC' - PD Get Source Capabilities
      7. 3.2.7 'SSrC' - PD Send Source Capabilities
    3. 3.3 Patch Bundle Update Tasks
      1. 3.3.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 3.3.2 'PBMc' - Patch Burst Mode Download Complete
      3. 3.3.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 3.3.4 Patch Burst Mode Example
      5. 3.3.5 'GO2P' - Go to Patch Mode
    4. 3.4 System Tasks
      1. 3.4.1 'DBfg' - Clear Dead Battery Flag
      2. 3.4.2 'I2Cr' - I2C Read Transaction
      3. 3.4.3 'I2Cw' - I2C Write Transaction
  5. 4User Reference
    1. 4.1 PD Controller Application Customization
    2. 4.2 Loading a Patch Bundle
  6. 5Revision History

2.11 0x33 TX_SINK_CAPS Register

The PD controller transmits the contents of this register as a Sink_Capabilities message after receiving a Get_Sink_Cap message unless its configuration or USB PD rules require a different response in the context.

Note:

Writes to this register have no immediate effect. The PD controller updates and uses this register each time it must send a Sink Capabilities message.

Table 2-24 0x33 TX_SINK_CAPS Register
AddressNameAccessLengthUnique Per PortPower-Up Default
0x33TX_SINK_CAPSRW29yesInitialized by Application Configuration
Table 2-25 0x33 TX_SINK_CAPS Register Bit Field Definitions
BitsNameDescription
Bytes 26-29: PDO #7 (treated as a 32-bit little endian value)
31:0TXSinkPDO7Seventh Sink Capabilities PDO contents. See Table 2-27.
Bytes 22-25: PDO #6 (treated as a 32-bit little endian value)
31:0TXSinkPDO6Sixth Sink Capabilities PDO contents. See Table 2-27.
Bytes 18-21: PDO #5 (treated as a 32-bit little endian value)
31:0TXSinkPDO5Fifth Sink Capabilities PDO contents. See Table 2-27.
Bytes 14-17: PDO #4 (treated as a 32-bit little endian value)
31:0TXSinkPDO4Fourth Sink Capabilities PDO contents. See Table 2-27.
Bytes 10-13: PDO #3 (treated as a 32-bit little endian value)
31:0TXSinkPDO3Third Sink Capabilities PDO contents. See Table 2-27.
Bytes 6-9: PDO #2 (treated as a 32-bit little endian value)
31:0TXSinkPDO2Second Sink Capabilities PDO contents. See Table 2-27.
Bytes 2-5: PDO #1 (treated as a 32-bit little endian value)
31:0TXSinkPDO1First Sink Capabilities PDO contents. See Table 2-26.
Byte 1: Header
7:3Reserved
2:0numValidPDOs
(1) This feature is not supported by TPS25750_F509.04.02.
(2) This feature is not supported by TPS25750_F509.04.02.
(1) This feature is not supported by TPS25750_F509.05.02.

Each PDO in this TX_SINK_CAPS register follows the definition from the USB PD specification, reproduced below for convenience. For more details on the meaning of each field refer to the USB PD specification.

Table 2-26 First PDO
Bits(s)Description
31:30Supply Type, this shall always be set to 00b (Fixed Supply)
29Dual-Role Power, this is overridden by the logical OR of the ProcessSwapToSink, ProcessSwapToSource, InitiateSwapToSink, and InitiateSwapToSource fields in the PORT_CONTRL register.
28Higher Capability
27:26 Reserved
25Dual-Role Data, this is overridden by the logical OR of the ProcessSwapToUFP, ProcessSwapToDFP, InitiateSwapToUFP, and InitiateSwapToDFP fields in the PORT_CONTRL register.
24:20Reserved
19:10Voltage
9:0Operational Current
Table 2-27 Other PDO's.
Bits(s)Description
Fixed SupplyVariable SupplyBattery SupplyAPDO (PPS)
31:3000b01b10b11b
29:28Reserved.Maximum VoltageMaximum Voltage00b
27:25Reserved
24:20MaxPpsVoltage
19:17VoltageMinimum VoltageMinimum Voltage
16Reserved
15:10MinPpsVoltage
9:8Operational CurrentOperational CurrentOperational Power
7Reserved
6:0MaxPpsCurrent