Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must not be supplied before VCCA. A load switch supplies VIO_IN in this PDN. This load switch also supplies the VDDSHVx_MCU voltage domain of the processor. This allows PMIC GPIO control signals referenced to VIO_IN to remain active during MCU Only low power mode and to be disabled during DDR Retention (aka Suspend-to-RAM) to reduce PMIC power.

For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS659411-Q1 device can be used. A processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU processor to establish I2C communication with the PMICs during boot from SD card operations.

This PDN uses four discrete power components with three being required and one is optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The TPS62813-Q1 Buck Converter supplies LPDDR4 SDRAM component with required 1.1V supply. The unused primary PMIC FB pin, FB_B3, has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_DDR_1V1 power rail if an end product OV/UV monitoring requirements include this supply. The one optional discrete power component is TLV73318-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor VPP pins treated per data manual recommendations.

Figure 3-1 Power Connections

• * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
• ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD.

Table 3-1 identifies which power resources are required to support different system features. If the system feature listed is not required, the power resource connection can be removed and the processor voltage domains need to be grouped into alternative power rails.