SLVUC32B
June 2021 – February 2022
DRA829V
,
TDA4VM
,
TDA4VM-Q1
,
TPS6594-Q1
Trademarks
1
Introduction
2
Device Versions
3
Processor Connections
3.1
Power Mapping
3.2
Control Mapping
4
Supporting Functional Safety Systems
4.1
Achieving ASIL-B System Requirements
4.2
Achieving up to ASIL-D System Requirements
5
Static NVM Settings
5.1
Application-Based Configuration Settings
5.2
Device Identification Settings
5.3
BUCK Settings
5.4
LDO Settings
5.5
VCCA Settings
5.6
GPIO Settings
5.7
Finite State Machine (FSM) Settings
5.8
Interrupt Settings
5.9
POWERGOOD Settings
5.10
Miscellaneous Settings
5.11
Interface Settings
5.12
Multi-Device Settings
5.13
Watchdog Settings
6
Pre-Configurable Finite State Machine (PFSM) Settings
6.1
Configured States
6.2
PFSM Triggers
6.3
Power Sequences
6.3.1
TO_SAFE_SEVERE and TO_SAFE
6.3.2
TO_SAFE_ORDERLY and TO_STANDBY
6.3.3
ACTIVE_TO_WARM
6.3.4
ESM_SOC_ERROR
6.3.5
PWR_SOC_ERROR
6.3.6
MCU_TO_WARM
6.3.7
TO_MCU
6.3.8
TO_ACTIVE
6.3.9
To Suspend-to-RAM (TO_S2R)
7
Impact of NVM Changes
8
References
9
Revision History
6.3
Power Sequences