SLVUCI2 march   2023 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TPS6594-Q1

 

  1.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  2.   Trademarks
  3. 1Introduction
  4. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  5. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  6. 4Static NVM Settings.
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  7. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  8. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  9. 7References

5.3.9 TO_RETENTION

The C and D triggers, defined by the NSLEEPx bits or pins, trigger the TO_RETENTION sequence. This sequence disables all power rails and GPIOs that are not supplying the retention rails, as described in Figure 2-1. The sequence can be modified using the I2C_5 and I2C_7 bits found in register FSM_I2C_TRIGGERS. These bits need to be set by I2C in the PMIC before a trigger for the retention state occurs. If the I2C_7 bit is set high, the PMIC enters the DDR retention state. If the I2C_5 bit is set high, the PMIC enters the GPIO retention state. The TO_RETENTION sequence with both GPIO and DDR retention is shown in Figure 5-13. If I2C_5 and I2C_7 are set low, the components associated with DDR and GPIO retention do not remain active, as shown in Figure 5-12.

Note: The I2C_5 and I2C_7 bits need to be set or cleared by I2C in the PMIC before a trigger to the retention state occurs. The triggers are not self-clearing and must be maintained during operation.

GUID-20230131-SS0I-P27V-HBN3-B4QXZP5SNVKM-low.svgFigure 5-12 TO_RETENTION when I2C_5 and I2C_7 are Low
GUID-20221012-SS0I-PNLV-MF0P-G2TB36CTT302-low.svgFigure 5-13 TO_RETENTION when I2C_5 and I2C_7 are High

At the end of the sequence, the PMIC set the LPM_EN and clear the AMUXOUT_EN. The TPS6594133A device also performs an additional 16 ms delay based upon the contents of the register PFSM_DELAY_REG_2.