SLVUCI2 march   2023 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TPS6594-Q1

 

  1.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  2.   Trademarks
  3. 1Introduction
  4. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  5. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  6. 4Static NVM Settings.
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  7. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  8. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  9. 7References

4.3 BUCK Settings

These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in Section 5.3.

After the Section 5.3.8 sequence has completed, the BUCKx_EN bit is set for BUCK1, BUCK3, BUCK4, and BUCK5 in the TPS6594133A. The BUCKx_RV_SEL bit is cleared for all BUCKs. The other bits remain unchanged, but they are still accessible via I2C.

Table 4-3 BUCK NVM Settings
Register Name Field Name TPS6594
Value Description
BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator
BUCK1_FPWM 0x0 PFM and PWM operation (AUTO mode).
BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding.
BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators.
BUCK1_VSEL 0x0 BUCK1_VOUT_1
BUCK1_PLDN 0x1 Enabled; Pull-down resistor
BUCK1_RV_SEL 0x1 Enabled
BUCK1_CONF BUCK1_SLEW_RATE 0x4 2.5 mV/μs
BUCK1_ILIM 0x5 5.5 A
BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator
BUCK2_FPWM 0x0 PFM and PWM operation (AUTO mode).
BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators.
BUCK2_VSEL 0x0 BUCK2_VOUT_1
BUCK2_PLDN 0x1 Enabled; Pull-down resistor
BUCK2_RV_SEL 0x1 Enabled
BUCK2_CONF BUCK2_SLEW_RATE 0x4 2.5 mV/μs
BUCK2_ILIM 0x5 5.5 A
BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator
BUCK3_FPWM 0x0 PFM and PWM operation (AUTO mode).
BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding.
BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators.
BUCK3_VSEL 0x0 BUCK3_VOUT_1
BUCK3_PLDN 0x1 Enabled; Pull-down resistor
BUCK3_RV_SEL 0x1 Enabled
BUCK3_CONF BUCK3_SLEW_RATE 0x4 2.5 mV/μs
BUCK3_ILIM 0x5 5.5 A
BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator
BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode).
BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators.
BUCK4_VSEL 0x0 BUCK4_VOUT_1
BUCK4_PLDN 0x1 Enabled; Pull-down resistor
BUCK4_RV_SEL 0x1 Enabled
BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs
BUCK4_ILIM 0x5 5.5 A
BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator
BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode).
BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators.
BUCK5_VSEL 0x0 BUCK5_VOUT_1
BUCK5_PLDN 0x1 Enable Pull-down resistor
BUCK5_RV_SEL 0x1 Enabled
BUCK5_CONF BUCK5_SLEW_RATE 0x4 2.5 mV/μs
BUCK5_ILIM 0x3 3.5 A
BUCK1_VOUT_1 BUCK1_VSET1 0x73 1.10 V
BUCK1_VOUT_2 BUCK1_VSET2 0x73 1.10 V
BUCK2_VOUT_1 BUCK2_VSET1 0x73 1.10 V
BUCK2_VOUT_2 BUCK2_VSET2 0x73 1.10 V
BUCK3_VOUT_1 BUCK3_VSET1 0x41 0.850 V
BUCK3_VOUT_2 BUCK3_VSET2 0x41 0.850 V
BUCK4_VOUT_1 BUCK4_VSET1 0xb2 1.80 V
BUCK4_VOUT_2 BUCK4_VSET2 0xb2 1.80 V
BUCK5_VOUT_1 BUCK5_VSET1 0x41 0.850 V
BUCK5_VOUT_2 BUCK5_VSET2 0x41 0.850 V
BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV
BUCK1_UV_THR 0x3 -5% / -50 mV
BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV
BUCK2_UV_THR 0x3 -5% / -50 mV
BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV
BUCK3_UV_THR 0x3 -5% / -50 mV
BUCK4_PG_WINDOW BUCK4_OV_THR 0x3 +5% / +50 mV
BUCK4_UV_THR 0x3 -5% / -50 mV
BUCK5_PG_WINDOW BUCK5_OV_THR 0x3 +5% / +50 mV
BUCK5_UV_THR 0x3 -5% / -50 mV