Figure 2-4 shows the digital control signal mapping for PDN-3A between the PMIC, discrete power resources, and the processor. These connections enable a full feature system including MCU Only, DDR and GPIO Retention low power modes, functional safety up to ASIL-D, and compliant USB2.0, UHS-I SD card, and HS SoC eFuse programming on-board.

In this PDN, GPIO8 has been designed to provide run-time PDN configuration resulting in a flexible PMIC that adapts to each board design. A logic low input at the beginning of the power up sequence commands the PMIC to support isolated MCU and Main power groups which includes BUCK5 in the power up sequence. A logic high commands the PMIC to group MCU & Main power groups and exclude BUCK5 from power sequences. For isolated PDN scheme (variants A - F), the GPIO8 pin is connected to HCPS buck enable inputs which have a pull-up resistor to the input voltage of each buck. The VDA_DLL_0V8 power rail (sourced from LDO3 of the PMIC) is enabled at the same time stamp as the CPU & CORE rails. Therefore, it can be used to drive the input to a low voltage translator with an open-drain output that connects to HCPS enable net (MAIN_PWRGRP_IRQn). This buck pin is bi-directioinal and acts as both an enable input and status output. Internal buck faults result in the pin pulling the MAIN_PWRGRP_IRQn net low. Pulling the MAIN_PWRGRP_IRQn net low disables the buck and asserts an interrupt to PMIC via GPIO8 net connection. If GPIO8 goes low, the PMIC reacts as if SOC_PWR_ERROR has occurred causing a PDN state transition to MCU Only mode.

After the nRSTOUT PMIC signal goes high at the end of the TO_ACTIVE Sequence shown in Figure 5-11, GPIO10 is pulled high awaiting an active low MCU_PWRGRP_IRQn interrupt signal from the SVS-B voltage monitor. If GPIO10 goes low, the PMIC reacts as if an MCU_PWR_ERROR has occurred and executes an orderly shutdown. As shown in Figure 2-4, connect GPIO8 and GPIO10 with a 3.3V level translator from VDA_DLL_0V8 (PMIC LDO3) and the open drain interrupt outputs from voltage monitors SVS-A and SVS-B, respectively.

Other digital connections from the PMIC to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to maintain proper operation during low power modes when only a few GPIO pins remain operational.

Figure 2-4 TPS6594133A Digital Connections for PDN-3A

1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. For more information, see the device data sheet. The PMIC voltage domains indicated are for the TPS6594133A NVM configuration.
2. PMIC_Wake1 is typically a CAN PHY INH output.
3. LP_WKUP1 and WKUP1 transition to the ACTIVE state.

Use Table 2-5 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguration is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). For details on how functional safety related connections help achieve functional safety system-level goals, see Section 3.