SLVUCJ9 February   2023 LP8764-Q1 , TPS6594-Q1

 

  1.   PDN-0A User's Guide for Powering J7AEP with the TPS6594-Q1 and LP8764-Q1 PMICs
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Exiting LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

7 Application Examples

This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I2C. #GUID-6E2B7455-AA91-405A-A76F-9A975B1FBE13/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C shows how the I2C commands are presented in the following sections. These examples, when used in conjunction with the data sheet, can be generalized and applied to other use cases.

Table 7-1 I2C Instruction Format
I2C AddressRegister AddressDataMask
Write0x48, 0x4C or 0x580x00 - 0xFF0x00 - 0xFF0x00 - 0xFF
Read0x48, 0x4C or 0x580x00 - 0xFFNANA
Note: When the MASK is non-zero, this assumes a read has taken place and then a logical operation applied to only change the desired bit fields before writing the data back.