The TO_MCU sequence first turns off rails and GPIOs which are assigned to the SOC power group. The sequence enables the MCU rails, in the event that they are not already active (when transitioning from STANDBY to MCU_ONLY for example). This sequence can be changed based off the value stored in the I2C_6 and I2C_7 register bit of all PMICs. The I2C_6 and I2C_7 settings must be the same in each PMIC before triggering the sequence. If the I2C_7 bits are low, then EN_DDR_VDD1 and VDD_DDR_1V1 are disabled; If the I2C_6 bits are low, then VDD_GPIORET_3V3 and VDD_WK_0V8 are disabled as seen in #FIG_TVT_YZH_MQB. If the I2C_7 bits are high, then EN_DDR_VDD1 and VDD_DDR_1V1 are enabled; If the I2C_6 bits are high, then VDD_GPIORET_3V3 and VDD_WK_0V8 are enabled as seen in #FIG_LVC_SZH_MQB.

The first instructions of the TO_MCU sequence perform writes to the MISC_CTRL and ENABLE_DRV_STAT registers.

// TPS65941120
// Set AMUXOUT_EN, CLKMON_EN
// Clear LPM_EN, NRSTOUT_SOC 
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE1
// Clear SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
// TPS65941421
// Set AMUXOUT_EN, CLKMON_EN
// Clear LPM_EN 
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3
// Clear SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
// LP876411B5
// Set CLKMON_EN
// Clear LPM_EN 
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x08 MASK=0xF3
// Clear SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF

The last instructions of the TO_MCU sequence also perform writes to the MISC_CTRL and ENABLE_DRV_STAT registers after the delay defined in the PFSM_DELAY_REG_1.

// TPS659411120
SREG_READ_REG ADDR=0xCD REG=R1
DELAY_SREG R1
// Clear FORCE_EN_DRV_LOW 
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xF7
// Set NRSTOUT (MCU_PORZ)
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE