SLVUCR9C August   2023  – April 2025 TPS2HCS10-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Assembly Instructions
    2. 2.2 Revision Differences
    3. 2.3 Jumper Information
    4. 2.4 Interfaces
    5. 2.5 Test Points
    6. 2.6 Transient Testing
  9. 3Software
    1. 3.1 Software Usage
      1. 3.1.1  Command Center View
      2. 3.1.2  I2T Tuner
      3. 3.1.3  Device Settings
      4. 3.1.4  Channel Settings
      5. 3.1.5  Console View
      6. 3.1.6  Log View
      7. 3.1.7  Importing/Exporting
      8. 3.1.8  Firmware Updates
      9. 3.1.9  Persist Settings
      10. 3.1.10 Language Settings
    2. 3.2 Software Development
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

PCB Layouts

TPS2HCS10-Q1 HSS-HCMOTHERBRDEVM Top Layer

TPS2HCS10-Q1 HSS-HCMOTHERBRDEVM Power Layer Figure 4-4 HSS-HCMOTHERBRDEVM Power Layer

Figure 4-4 HSS-HCMOTHERBRDEVM Top Layer

TPS2HCS10-Q1 HSS-HCMOTHERBRDEVM Ground Layer Figure 4-6 HSS-HCMOTHERBRDEVM Ground Layer
TPS2HCS10-Q1 HSS-HCMOTHERBRDEVM Bottom Layer Figure 4-7 HSS-HCMOTHERBRDEVM Bottom Layer
TPS2HCS10-Q1 HSS-HCMOTHERBRDEVM 3D Plot Figure 4-8 HSS-HCMOTHERBRDEVM 3D Plot
TPS2HCS10-Q1 Daughter Card Top
                        LayerFigure 4-9 Daughter Card Top Layer
TPS2HCS10-Q1 Daughter Card GND
                        LayerFigure 4-11 Daughter Card GND Layer
TPS2HCS10-Q1 Daughter Card 3D
                        PlotFigure 4-13 Daughter Card 3D Plot
TPS2HCS10-Q1 Daughter Card Power
                        LayerFigure 4-10 Daughter Card Power Layer
TPS2HCS10-Q1 Daughter Card Bottom
                        LayerFigure 4-12 Daughter Card Bottom Layer