SLVUDA3 July   2025 MSPM0G3507

 

  1.   1
  2.   Description
  3.   Features
  4. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  5. 2Hardware
    1. 2.1 Hardware Features
      1. 2.1.1 MSPM0G3507 MCU
      2. 2.1.2 Application (or Backchannel) UART
      3. 2.1.3 Using an External Debug Probe
    2. 2.2 Power
    3. 2.3 Clocking
    4. 2.4 Pinout
  6. 3Hardware Design Files
    1. 3.1 Hardware Design Files
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  7. 4Software Examples
  8. 5Resources
    1. 5.1 Integrated Development Environments
      1. 5.1.1 TI Cloud Development Tools
      2. 5.1.2 TI Resource Explorer Cloud
      3. 5.1.3 Code Composer Studio Cloud
      4. 5.1.4 Code Composer Studio IDE
    2. 5.2 MSPM0 SDK and TI Resource Explorer
    3. 5.3 Community Resources
      1. 5.3.1 TI E2E Forums
  9. 6Additional Information
    1. 6.1 Trademarks
  10. 7Revision History

MSPM0G3507 MCU

The MSPM0G3507 devices provide 128KB of embedded flash program memory with built-in error correction code (ECC) and 32KB of SRAM with hardware parity. The devices also incorporate a memory protection unit, 7-channel DMA, math accelerator, and a variety of high-performance analog peripherals such as two 12-bit 4-Msps ADCs, a configurable internal shared voltage reference, one 12-bit DAC, three high speed comparators with built-in reference DACs, two zero-drift op-amps with programmable gain, and one general-purpose amplifier. The devices also offer intelligent digital peripherals such as two 16-bit advanced control timers, three 16-bit general purpose timers, one 32-bit high resolution timer, two windowed-watchdog timers, and one RTC with alarm and calendar mode. These devices provide data integrity and encryption peripherals (AES, CRC, TRNG) and enhanced communication interfaces (four UART, two I2C, two SPI, and one CAN 2.0/FD).

Device feature include:

  • 1.62V to 3.6V operation
  • Arm 32-bit Cortex-M0+ with memory protection unit, up to 80MHz
  • 128KB of flash with built-in ECC and 32KB of SRAM with hardware parity
  • Two 12-bit 4-Msps ADCs
  • 12-bit DAC
  • Two zero-drift zero-crossover chopper op-amps
  • Two 16-bit advanced control timers
  • Three 16-bit general-purpose timers
  • One 32-bit high-resolution time
  • 60 GPIO
 LQFP64 (VQFN) (Top
                    View) Figure 2-3 LQFP64 (VQFN) (Top View)