SLVUDB7 June   2025 TPS7H5020-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Primary Side Regulation
    2. 2.2 Connector Descriptions
    3. 2.3 Best Practices
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Soft Startup
    3. 3.3 Voltage Ripple on VOUT
    4. 3.4 Load Step
    5. 3.5 Frequency Response
    6. 3.6 Efficiency
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7Related Documentation

2.3 Best Practices

The following information is provided to convey best practices while operating this device.

TPS7H5020FLYEVM
WARNING:

Hot surface. Contact can cause burns. Do not touch.

Some components can reach high temperatures > 55°C when the board is powered on. Do not touch the board at any point during operation or immediately after operating, as high temperatures can be present.

CAUTION: The TPS7H5020FLYEVM uses separate power connectors for the power stage and controller power. When powering on the EVM, remember to supply power to the power stage though connectors J1 and J2 before powering (or enabling if using an external enable signal) the TPS7H5020 device. Reversing this order can cause the power stage to be shorted through the GaN FET, possibly causing damage to the EVM or lab equipment.