SLVUDB7 June   2025 TPS7H5020-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Primary Side Regulation
    2. 2.2 Connector Descriptions
    3. 2.3 Best Practices
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Soft Startup
    3. 3.3 Voltage Ripple on VOUT
    4. 3.4 Load Step
    5. 3.5 Frequency Response
    6. 3.6 Efficiency
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7Related Documentation

4.2 PCB Layouts

TPS7H5020FLYEVM Top Overlay Figure 4-3 Top Overlay
TPS7H5020FLYEVM Top Solder Mask Figure 4-4 Top Solder Mask
TPS7H5020FLYEVM Layer 1 (Top) Figure 4-5 Layer 1 (Top)
TPS7H5020FLYEVM Layer 2 Figure 4-6 Layer 2
TPS7H5020FLYEVM Layer 3 Figure 4-7 Layer 3
TPS7H5020FLYEVM Layer 4 (Bottom) Figure 4-8 Layer 4 (Bottom)
TPS7H5020FLYEVM Bottom Solder Mask Figure 4-9 Bottom Solder Mask
TPS7H5020FLYEVM Bottom Overlay Figure 4-10 Bottom Overlay
TPS7H5020FLYEVM Drill Drawing Figure 4-11 Drill Drawing