SLWU067D November   2009  – March 2022 ADS4122 , ADS4125 , ADS4126 , ADS4128 , ADS4129 , ADS4142 , ADS4145 , ADS4146 , ADS4149 , ADS41B25 , ADS41B29 , ADS41B49 , ADS58B18 , ADS58B19

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Purpose
    2. 1.2 EVM Quick-Start Procedure
  3. 2Circuit Description
    1. 2.1 Schematic Diagram
    2. 2.2 Circuit Function
      1. 2.2.1 Power
        1. 2.2.1.1 Power Supply Option 1
        2. 2.2.1.2 Power Supply Option 2
        3. 2.2.1.3 Power Supply Option 3
      2. 2.2.2 Clock Input
        1. 2.2.2.1 Clock Option 1
        2. 2.2.2.2 Clock Option 2
        3. 2.2.2.3 Clock Option 3
      3. 2.2.3 Analog Inputs
        1. 2.2.3.1 Analog Input Option 1
        2. 2.2.3.2 Analog Input Option 2
      4. 2.2.4 Digital Outputs
  4. 3TI ADC SPI Control Interface
    1. 3.1 Installing the ADC SPI Interface
    2. 3.2 Setting Up the EVM for ADC SPI Control
    3. 3.3 Using the TI ADC SPI Interface Software
      1. 3.3.1 SPI Register Writes
  5. 4Quick Start Setup
  6. 5Evaluation
    1. 5.1 Register Programming
    2. 5.2 Quick-Test Results

2.2.4 Digital Outputs

The LVDS digital outputs can be accessed through the J10 output connector. A parallel 100-Ω termination resistor must be placed at the receiver to properly terminate each LVDS data pair. These resistors are required if the user wants to analyze the signals on an oscilloscope or a logic analyzer. The ADC performance also can be quickly evaluated using the TSW1400 board along with the High Speed Data Converter Pro software as explained in the next section. The TSW1400 automatically terminates the LVDS outputs once the TSW1400 is connected to J10. Alternatively, the ADS41xx/58B18 is supplied with a breakout-board to easily connect the LVDS outputs to a logic analyzer pod. This LVDS breakout-board also properly terminates the LVDS outputs once the breakout board is connected to J10.

The ADS41xx and most other ADCs that may be evaluated on this EVM also have an option to output the digitized parallel data in the form of single-ended CMOS. If single-ended CMOS is desired, header post connector J5 is provided for the CMOS output. In order to use the header J5, a CMOS buffer U7 must be installed in place of a bank of 0-Ω resistors that by default steer the outputs to the LVDS connector J10.