5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)

This section describes the operation when testing with a DAC5688EVM that has a CMOS input interface.

• Power down the TSW1400 if the DAC5688EVM is not installed.

NOTE

J1 pin 1 of the TSW1400 connector plugs into J2 pin 1 on the DAC5688EVM

• Provide unpowered +3.3 VDC connections to J15 and return to J16 of the DAC5688EVM.
• Provide unpowered +1.8 VDC connections to J13 and return to J14 of the DAC5688EVM.
• Provide a USB cable between the DAC5688EVM and a host PC.
• Provide an external sinewave source at 491.52 MHz with a 1-Vrms, 0-V offset to SMA J20 (EXT_VCXO) of the DAC5688EVM.
• Connect a SMA cable from OUTCLK3 connector (J17) of the DAC5688EVM to CMOS_CLK (J7) of the TSW1400 EVM.
• Power up the TSW1400 followed by the DAC EVM.
• Load and start up the DAC5688EVM GUI as described in the DAC5688EVM User’s Guide. The software and User’s Guide can be found at http://www.ti.com/tool/dac5688evm.

• Start up the HSDC Pro GUI as described in the Software Start Up section.
• The TSW1400 EVM connected to the CMOS connectors of the DAC5688EVM is shown in Figure 16.

Using the DAC5688EVM GUI, load the EVM with the test file called “example”. This can be found at C:\Program Files\Texas Instruments\DAC5688\DAC5688 Configuration Files. This sets up the DAC5688 to receive a WCDMA test pattern from the TSW1400 with a data rate of 122.88 MHz. CLK2 of DAC5688 operates at 491.52 MHz and the DAC interpolation is set to 4x, requiring the input data rate to be at 122.88 MHz.

In the DAC5688 GUI, go to the CDCM7005 tab and set the Y3 Output (OUTCLK3) to divide by 4, LVCMOS, and inverting per Figure 17.

This generates an inverted 122.88-MHz clock used by the TSW1400 to generate the CMOS test pattern.

NOTE

The CMOS data rate for the TSW1400 EVM should never exceed 250 MHz. This rate is set by the CMOS_CLOCK input provide to J7. When operating at frequencies near this limit, the user may need to adjust the delay of this signal to meet the timing specs of the DAC under test.

On the DAC5688EVM, there is an option to use a spare output of the CDCM7005 clock generator as a clock source. In this example, the OUTCLK3 of the CDCM7005 is inverted for optimized setup and hold time. Another way to adjust the delay is to use different cable lengths for this clock source.

If opening the HSDC Pro GUI for the first time, when setting up for pattern generator mode, make sure “DAC” in the top right side of the GUI is selected. This targets the EVM for this test example. In the “Select DAC” button of the GUI, click on the drop down arrow and select “cmos”. This firmware is used by most High Speed CMOS DAC EVMs.

Click on “Yes” when asked “Do you want to update the firmware for DAC”. The firmware setup is loaded during this process, which takes approximately 20 seconds. After the firmware load has completed, the LEDs labeled USER_LED (0–7) will now turn on except for USER_LED 5. USER_LED 3 is used to indicate the status of a second PLL, and USER_LED 5 indicates if there is a FIFO overflow (error) of the transmit data.

NOTE

If the TSW1400 is not receiving a valid clock from the DAC EVM, USER_LED3 and USER_LED4 are off.

For this test, at the top of the GUI, set the following parameters:

• Preamble to 0
• Data Rate – 122.88M (MSPS)
• DAC Option – 2’s Comp
• Active Channel – Channel 1
• Format – Complex
• Analysis Window (samples) - 65536
• Click on the button labeled “Load File to transfer into TSW1400”.
• Select “WCDMA_TM1_complexIF30MHz_Fdata122.88MHz_1000.csv”.
• Click on “Send”.

The display panel of the GUI is updated, showing the test data that is transmitted to the DAC EVM in both codes and frequency domain as shown in Figure 18.

If the DAC5688EVM is configured for IF output, connect a spectrum analyzer to either SMA J4 (IOUTB2) or J9 (IOUTA2) of the EVM. The DAC example file has a NCO setting of 61.44 MHz and the test pattern IF is centered at 30 MHz. The signal should be a single carrier centered around 91.44 MHz, as shown in Figure 19.

NOTE

The DAC5688EVM has the default setup as RF output. The modulator output location will be at the LO frequency plus 91.44 MHz. For details about IF and RF output configuration settings, see section 4.7 of the DAC5688EVM User’s Guide (SLAU241).