SLWU086C November   2013  – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84

 

  1.   TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
      2. 2.2 Switches, Jumpers, and LEDs
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
      3. 2.3 LEDs
        1. 2.3.1 Power and Configuration LEDs
        2. 2.3.2 Status LEDs
        3. 2.3.3 Connectors
          1. 2.3.3.1 SMA Connectors
          2. 2.3.3.2 FPGA Mezzanine Card (FMC) Connector
          3. 2.3.3.3 JTAG Connectors
          4. 2.3.3.4 USB I/O Connection
    4. 3 Software Start-Up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
    5. 4 Downloading Firmware
  2.   Revision History

2.3.3.1 SMA Connectors

The TSW14J56 has 9 SMA connectors. The connectors are defined below:

J6 GBTCLK0N Spare Transceiver reference clock negative input
J5 GBTCLK0P Spare Transceiver reference clock positive input
J13 TRIG_IN Adjustable level CMOS trigger input. Default level is 1.8 V
J7 TRIG_OUT_A Adjustable level CMOS trigger output. Default level is 1.8 V
J8 TRIG_OUT_B Adjustable level CMOS trigger output. Default level is 1.8 V
J12 TRIG_OUT_C Adjustable level CMOS trigger output. Default level is 1.8 V
J3 REF_OSC_IN AC coupled spare input connected to FPGA CLK input
J14 EXT_SYSREFP Spare SYSREF positive input to FPGA
J15 EXT_SYSREFN Spare SYSREF negative input to FPGA