2 What is process gain?

Earlier forms of high-speed signal chain line ups involved ADCs that used to consume watts of power per single channel, and FPGAs (field-programmable gate array) which captured, filtered and processed all converter data into some useful format. Most designers would use an approach called process gain. This approach not only helped in frequency planning by eliminating unwanted spurious and noise; it also enabled the ability to “gain” dynamic range in terms of the signal-to-noise ratio (SNR) by limiting the bandwidth processed within the Nyquist zone. Adding the process gain correction factor to the standard SNR equation results in Equation 2:

where N is the number of ADC bits, Fs is the ADC sampling frequency and BW is the bandwidth of interest within the Nyquist zone.

With smaller process nodes deployed into both ADC and digital-to-analog converter technology, much of the standard FPGA digital features now reside within the ADC. Some examples include digital downconverters (DDCs), numerically controlled oscillators (NCOs) and frequency hopping. These features significantly help offload FPGA processing, making it possible to use its internal resources elsewhere.