SLYT866 May   2025 ADC32RF52 , ADC32RF54 , ADC32RF55 , ADC32RF72 , ADC34RF52 , ADC34RF55 , ADC34RF72 , ADC3548 , ADC3549 , ADC3568 , ADC3569 , ADC3648 , ADC3649 , ADC3668 , ADC3669

 

  1.   1
  2.   2
  3. 1Nyquist rules
  4. 2What is process gain?
  5. 3Why frequency plan?
  6. 4Common pitfalls in frequency planning
  7. 5Advantages of proper frequency planning using decimation
  8. 6Theoretical example: Frequency planning with decimation
  9. 7Real World Examples: Frequency planning with decimation
  10. 8Conclusion
  11. 9Related Websites

Why frequency plan?

Proper frequency planning is an important step when designing systems using ADCs. Frequency planning ensures efficient utilization of the ADC’s dynamic range and minimizes unwanted spurious signals, which are crucial for high-performance applications such as SDR systems or high-density RF signal chains.

One essential aspect of frequency planning is optimizing the ADC’s dynamic range. Each additional signal in the analog domain consumes part of the ADC’s available input signal power budget, reducing the total dynamic range capability. Proper frequency planning ensures that the ADC fully exercises its capabilities by strategically placing input frequencies to maximize the usable dynamic range. This approach involves considering where unwanted spurs and harmonics will appear in the sampled band, ensuring that there is no overlap between the signals of interest and spurious components.

Another critical aspect is managing the inherent spurious signals generated by ADCs, such as harmonics and interleaving artifacts. A frequency plan is successful when these spurious contributions remain out of the intended band, especially in systems that do not employ digital filtering after the data is sampled. Frequency planning also helps minimize the impact of clocking-related spurs, such as those that appear from clocking devices lacking channel isolation, which are particularly problematic in large element systems that use a high-density clock distribution solution.

Interleaving spur management is also a consideration in systems containing an interleaved ADC, where multiple ADC cores sample a common input signal orthogonally, effectively doubling the sampling rate and Nyquist region by a factor of two. This interleaving introduces spurious tones at Fs/2-Fin, however. Additionally, in systems that use higher interleaving factors, this same Fs/2-Fin spur is modulated once again by the “new” Fs/2-Fin. This results in the new Fin being comprised of the interleaved Fs/2-Fin spur, meaning that the spur count introduced is much higher than a single interleaving factor. Frequency planning enables you to mitigate these spurs by leveraging analog filtering or (preferably) digital decimation filters, attenuating them significantly without having to design a complex analog signal chain. While this approach reduces the instantaneous bandwidth to a selected region, it ensures better dynamic range and cleaner signal performance.