SLYY234 December 2024 AMC0106M05 , AMC0106M25 , AMC0136 , AMC0311D , AMC0311S , AMC0386 , AMC0386-Q1 , AMC1100 , AMC1106M05 , AMC1200 , AMC1200-Q1 , AMC1202 , AMC1203 , AMC1204 , AMC1211-Q1 , AMC1300 , AMC1300B-Q1 , AMC1301 , AMC1301-Q1 , AMC1302-Q1 , AMC1303M2510 , AMC1304L25 , AMC1304M25 , AMC1305M25 , AMC1305M25-Q1 , AMC1306M05 , AMC1306M25 , AMC1311 , AMC1311-Q1 , AMC131M03 , AMC1336 , AMC1336-Q1 , AMC1350 , AMC1350-Q1 , AMC23C12 , AMC3301 , AMC3330 , AMC3330-Q1
The schematic used in testing is the same as the ferrite section of Figure 67. However, layout for stacking the AMC3301’s is shown in Figure 67.
Figure 67 Recommended Multiple AMC3301
Devices LayoutIn general, the same layout principles described in Section 6.2.3.2 are followed with a two layer board design.
However, a direct and low inductance path from pin 2 (DCDC_HGND) to pin 8 (HGND) of each device is achieved differently. Instead of a trace, a star connection connects both devices between the top and bottom layers at pins 4 and 5. In addition, a pool of copper is used to connect the DC/DC capacitors to DCDC_HGND on the same layer.
Finally, the LDO_OUT capacitors are scaled up to a 1206 package to allow direct and uninterrupted path for the positive and negative inputs underneath the capacitors.