SNAA435 April   2025 CDC6C-Q1 , LMK3C0105-Q1 , LMK3H0102-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2FPD-Link REFCLK Requirements and Jitter Definitions
    1. 2.1 FPD-Link III REFCLK Requirements
    2. 2.2 FPD-Link IV REFCLK Requirements
  6. 3FPD-Link Clocking Selection Guide
  7. 4EMI Considerations
  8. 5Summary
  9. 6References

2.2 FPD-Link IV REFCLK Requirements

All FPD-Link IV devices share the same 1.5ps RMS (12kHz - 20MHz integration range) maximum frequency-domain jitter limit. The REFCLK input is generally 25MHz for camera (ADAS) SerDes and 27MHz for display (IVI) SerDes.