SNAS717A April   2017  – October 2021 ADC12D1620QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristic: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Electrical Characteristics: Delta Parameters
    15. 6.15 Timing Requirements: Serial Port Interface
    16. 6.16 Timing Requirements: Calibration
    17. 6.17 Quality Conformance Inspection
    18. 6.18 Timing Diagrams
    19. 6.19 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Operation Summary
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Control and Adjust
        1. 7.3.1.1 AC- and DC-Coupled Modes
        2. 7.3.1.2 Input Full-Scale Range Adjust
        3. 7.3.1.3 Input Offset Adjust
        4. 7.3.1.4 Low-Sampling Power-Saving Mode (LSPSM)
        5. 7.3.1.5 DES Timing Adjust
        6. 7.3.1.6 Sampling Clock Phase Adjust
      2. 7.3.2 Output Control and Adjust
        1. 7.3.2.1 SDR / DDR Clock
        2. 7.3.2.2 LVDS Output Differential Voltage
        3. 7.3.2.3 LVDS Output Common-Mode Voltage
        4. 7.3.2.4 Output Formatting
        5. 7.3.2.5 Test-Pattern Mode
        6. 7.3.2.6 Time Stamp
      3. 7.3.3 Calibration Feature
        1. 7.3.3.1 Calibration Control Pins and Bits
        2. 7.3.3.2 How to Execute a Calibration
        3. 7.3.3.3 On-Command Calibration
        4. 7.3.3.4 Calibration Adjust
          1. 7.3.3.4.1 Read/Write Calibration Settings
        5. 7.3.3.5 Calibration and Power-Down
        6. 7.3.3.6 Calibration and the Digital Outputs
      4. 7.3.4 Power Down
      5. 7.3.5 Low-Sampling Power-Saving Mode (LSPSM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DES/Non-DES Mode
      2. 7.4.2 Demux/Non-Demux Mode
    5. 7.5 Programming
      1. 7.5.1 Control Modes
        1. 7.5.1.1 Non-ECM
          1. 7.5.1.1.1  Dual-Edge Sampling Pin (DES)
          2. 7.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 7.5.1.1.3  Dual Data-Rate Phase Pin (DDRPh)
          4. 7.5.1.1.4  Calibration Pin (CAL)
          5. 7.5.1.1.5  Low-Sampling Power-Saving Mode Pin (LSPSM)
          6. 7.5.1.1.6  Power-Down I-Channel Pin (PDI)
          7. 7.5.1.1.7  Power-Down Q-Channel Pin (PDQ)
          8. 7.5.1.1.8  Test-Pattern Mode Pin (TPM)
          9. 7.5.1.1.9  Full-Scale Input-Range Pin (FSR)
          10. 7.5.1.1.10 AC- or DC-Coupled Mode Pin (VCMO)
          11. 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
        2. 7.5.1.2 Extended Control Mode
          1. 7.5.1.2.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Driving the ADC in DES Mode
        3. 8.1.1.3 FSR and the Reference Voltage
        4. 8.1.1.4 Out-Of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
        3. 8.1.3.3 Terminating Unused LVDS Output Pins
      4. 8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
      5. 8.1.5 Temperature Sensor
    2. 8.2 Radiation Environments
      1. 8.2.1 Total Ionizing Dose
      2. 8.2.2 Single Event Latch-Up and Functional Interrupt
      3. 8.2.3 Single Event Upset
    3. 8.3 Cold Sparing
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-On Considerations
      1. 9.1.1 Control Pins
      2. 9.1.2 Power On in Non-ECM
      3. 9.1.3 Power On in ECM
      4. 9.1.4 Power-on and Data Clock (DCLK)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Planes
      2. 10.1.2 Bypass Capacitors
      3. 10.1.3 Ground Planes
      4. 10.1.4 Power System Example
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Board Mounting Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

7.6.1 Register Definitions

Eleven read/write registers provide several control and configuration options in the extended control mode. When the device is in non-extended control mode (non-ECM), the registers have the settings shown in the "DV" rows and cannot be changed. See Table 7-12 for a summary.

Table 7-12 Register Addresses
A3A2A1A0HEXREGISTER ADDRESSED
00000hConfiguration Register 1
00011hReserved
00102hI-channel Offset Adjust
00113hI-channel Full-Scale Range Adjust
01004hCalibration Adjust
01015hCalibration Values
01106hReserved
01117hDES Timing Adjust
10008hReserved
10019hReserved
1010AhQ-channel Offset Adjust
1011BhQ-channel Full-Scale Range Adjust
1100ChAperture Delay Coarse Adjust
1101DhAperture Delay Fine Adjust
1110EhAutoSync
1111FhReserved
Table 7-13 Configuration Register 1
Addr: 0h (0000b)Default Values: 2000h
Bit1514131211109876543210
NameCALDPSOVSTPMPDIPDQResLFSDESDEQDIQ2SCTSESDRReserved
DV(1)00100000/100000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15CAL: Calibration enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration. TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance that an SEU causes a calibration cycle.
Bit 14DPS: DCLK phase select. In DDR, set this bit to 0b to select the 0° mode DDR data-to-DCLK phase relationship and to 1b to select the 90° mode. In SDR, set this bit to 0b to transition the data on the rising edge of DCLK; set this bit to 1b to transition the data on the falling edge of DCLK.
Bit 13OVS: Output voltage select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics for details.
Bit 12TPM: Test pattern mode. When this bit is set to 1b, the device continually outputs a fixed digital pattern at the digital data and OR outputs. When set to 0b, the device continually outputs the converted signal, which was present at the analog inputs. See Test-Patterm Mode for details about the TPM pattern.
Bit 11PDI: Power-down I channel. When this bit is set to 0b, the I channel is fully operational; when it is set to 1b, the I channel is powered-down. The I channel may be powered-down through this bit or the PDI pin, which is active, even in ECM.
Bit 10PDQ: Power-down Q channel. When this bit is set to 0b, the Q channel is fully operational; when it is set to 1b, the Q channel is powered-down. The Q channel may be powered-down through this bit or the PDQ pin, which is active, even in ECM.
Bit 9Reserved. Must be set as shown.
Bit 8LFS: Low-frequency select. If the sampling clock (CLK) is at or below 300 MHz in non-LSPSM, set this bit to 1b for improved performance. In LSPSM, the device is automatically in LFS, and this bit is inactive.
Bit 7DES: Dual-edge sampling mode select. When this bit is set to 0b, the device operates in the non-DES mode; when it is set to 1b, the device operates in the DES mode. See DES/Non-Des Mode for more information.
Bit 6DEQ: DES Q input select, also known as DESQ mode. When the device is in DES mode, this bit selects the input that the device operates on. The default setting of 0b selects the I input and 1b selects the Q input.
Bit 5DIQ: DES I and Q input, also known as DESIQ mode. When in DES mode, setting this bit to 1b shorts the I and Q inputs internally to the device. In this mode, both the I and Q inputs must be externally driven; see DES/Non-Des Mode for more information. If the bit is left at its default 0b, the I and Q inputs remain electrically separate.
The allowed DES modes settings are shown below. For DESCLKIQ mode, see the Table 7-27 register (Addr Eh).
MODEADDR 0h, BIT<7:5>ADDR Eh, BIT<6>
Non-DES mode000b0b
DESI mode100b0b
DESQ mode110b0b
DESIQ mode101b0b
DESCLKIQ mode000b1b
Bit 42SC: Two's complement output. For the default setting of 0b, the data is output in offset binary format; when set to 1b, the data is output in two's complement format.
Bit 3TSE: Time stamp enable. For the default setting of 0b, the time stamp feature is not enabled; when set to 1b, the feature is enabled. See Output Control and Adjust for more information about this feature.
Bit 2SDR: Single data rate. For the default setting of 0b, the data is clocked in dual data rate; when set to 1b, the data is clocked in single data rate. See Output Control and Adjust for more information about this feature. Note that for DDR mode, the 1:2 demux mode is not available in LSPSM. See Supported Demux , Data Rate Modes for a selection of available modes.
Bits 1:0Reserved. Must be set as shown.
Table 7-14 Reserved
Addr: 1h (0001b)Default Values: 2907h
Bit1514131211109876543210
NameReserved
DV(1)0010100100000111
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0Reserved. Must be set as shown.
Table 7-15 I-Channel Offset Adjust
Addr: 2h (0010b)Default Values: 0000h
Bit1514131211109876543210
NameReservedOSOM(11:0)
DV(1)0000000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:13Reserved. Must be set to 0b.
Bit 12OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs.
CODEOFFSET [mV]
0000 0000 0000 (default)0
1000 0000 000022.5
1111 1111 111145
Table 7-16 I-Channel Full Scale Range Adjust
Addr: 3h (0011b)Default Values: 4000h
Bit1514131211109876543210
NameResFM(14:0)
DV(1)0100000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15Reserved. Must be set to 0b.
Bits 14:0FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for characterization details.
CODEFSR [mV]
000 0000 0000 0000600
100 0000 0000 0000 (default)800
111 1111 1111 11111000
Table 7-17 Calibration Adjust
Addr: 4h (0100b)Default Values: DB4Bh
Bit1514131211109876543210
NameResCSSReservedSSCReserved
DV(1)1101101101001011
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15Reserved. Must be set as shown.
Bit 14CSS: Calibration sequence select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN calibration, do internal linearity calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity calibration).
Bits 13:8Reserved. Must be set as shown.
Bit 7SSC: SPI scan control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read/written. When not reading/writing the calibration values, this control bit should left at its default 0b setting. See Calibration Feature for more information.
Bits 6:0Reserved. Must be set as shown.
Table 7-18 Calibration Values
Addr: 5h (0101b)Default Values: XXXXh
Bit1514131211109876543210
NameSS(15:0)
DV(1)XXXXXXXXXXXXXXXX
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0SS(15:0): SPI scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may be read from/written to it. Set the SSC of the Calibration Adjust register (Addr: 4h, Bit: 7) to read/write. See Calibration Feature for more information.
Table 7-19 Reserved
Addr: 6h (0110b)Default Values: 1C2Eh
Bit1514131211109876543210
NameReserved
DV(1)0001110000101110
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0Reserved. Must be set as shown.
Table 7-20 DES Timing Adjust
Addr: 7h (0111b)Default Values: 8142h
Bit1514131211109876543210
NameDTA(6:0)Reserved
DV(1)1000000101000010
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:9DTA(6:0): DES mode timing adjust. In the DES mode, the time at which the falling edge sampling clock samples relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input Control and Adjust for more information. The nominal step size is 30 fs.
Bits 8:0Reserved. Must be set as shown.
Table 7-21 Reserved
Addr: 8h (1000b)Default Values: 0F0Fh
Bit1514131211109876543210
NameReserved
DV(1)0000111100001111
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0Reserved. Must be set as shown.
Table 7-22 Reserved
Addr: 9h (1001b)Default Values: 0000h
Bit1514131211109876543210
NameReserved
DV(1)0000000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0Reserved. Must be set as shown.
Table 7-23 Q-Channel Offset Adjust
Addr: Ah (1010b)Default Values: 0000h
Bit1514131211109876543210
NameReservedOSOM(11:0)
DV(1)0000000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:13Reserved. Must be set to 0b.
Bit 12OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude.
Bits 11:0OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs.
CODEOFFSET [mV]
0000 0000 0000 (default)0
1000 0000 000022.5
1111 1111 111145
Table 7-24 Q-Channel Full-Scale Range Adjust
Addr: Bh (1011b)Default Values: 4000h
Bit1514131211109876543210
NameResFM(14:0)
DV(1)0100000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bit 15Reserved. Must be set to 0b.
Bits 14:0FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for characterization details.
CODEFSR [mV]
000 0000 0000 0000600
100 0000 0000 0000 (default)800
111 1111 1111 11111000
Table 7-25 Aperture Delay Coarse Adjust
Addr: Ch (1100b)Default Values: 0004h
Bit1514131211109876543210
NameCAM(11:0)STADCCRes
DV(1)0000000000000100
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:4CAM(11:0): Coarse adjust magnitude. This 12-bit value determines the amount of delay that is applied to the input CLK signal. The range is 0-ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function.
Bit 3STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which makes both coarse and fine adjustment settings, that is, CAM(11:0) and FAM(5:0), available.
Bit 2DCC: Duty cycle correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature is enabled by default.
Bits 1:0Reserved. Must be set to 0b.
Table 7-26 Aperture Delay Fine Adjust
Addr: Dh (1101b)Default Values: 0000h
Bit1514131211109876543210
NameFAM(5:0)Reserved
DV(1)0000000000000000
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:10FAM(5:0): Fine aperture adjust magnitude. This 6-bit value determines the amount of additional delay that is applied to the input CLK when the clock phase adjust feature is enabled through STA (Addr: Ch; Bit: 3). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bits 9:0Reserved. Must be set as shown.
Table 7-27 AutoSync
Addr: Eh (1110b)Default Values: 0003h
Bit1514131211109876543210
NameDRC(8:0)DCKResSP(1:0)ESDOCDR
DV(1)0000000000000011
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:7DRC(8:0): Delay reference clock. These bits may be used to increase the delay on the input reference clock when synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1200 ps (319d). The delay remains the maximum of 1200 ps for any codes above or equal to 319d. See Synchronizing Multiple ADC12D1620 Devices in a System for more information.
Bit 6DCK: DESCLKIQ mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I and Q inputs 180° out of phase with respect to one , that is, the DESCLKIQ mode. To select the DESCLKIQ mode, Addr: 0h, Bits <7:5> must also be set to 000b. See Input Control and Adjust for more information.
Bit 5Reserved. Must be set as shown.
Bits 4:3SP(1:0): Select phase. These bits select the phase of the reference clock that is latched. The codes correspond to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2ES: Enable secondary. Set this bit to 1b to enable the secondary mode of operation. In this mode, the internal divided clocks are synchronized with the reference clock coming from the primary ADC. The primary clock is applied on the input pins RCLK. If this bit is set to 0b, then the device is in primary mode.
Bit 1DOC: Disable output reference clocks. In non-LSPSM, setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2; in LSPSM, setting this bit to 0b sends a CLK/2 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in primary or secondary mode, as determined by ES (Bit 2).
Bit 0DR: Disable reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality.
Table 7-28 Reserved
Addr: Fh (1111b)Default Values: 001Dh
Bit1514131211109876543210
NameReserved
DV(1)0000000000011101
(1) DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values.
Bits 15:0Reserved. This address is read only.