SNAU266A July   2021  – August 2022

 

  1.   Abstract
  2. 1First-Time Setup
    1. 1.1 Evaluation Module Contents
    2. 1.2 Evaluation Setup Requirements
  3. 2EVM Connections
    1. 2.1 Connection Diagram
    2. 2.2 Power Supply
    3. 2.3 Reference Clock
    4. 2.4 Output Connections
    5. 2.5 Programming Interface
  4. 3Feature Evaluation
    1. 3.1 Buffer, Divider, and Multiplier Modes
    2. 3.2 SYSREF Generation
    3. 3.3 SYSREF Delay Generators
  5. 4Schematic
  6. 5PCB Layout and Layer Stack-Up
    1. 5.1 PCB Layer Stack-Up
    2. 5.2 PCB Layout
  7. 6Bill of Materials
  8.   A Troubleshooting
  9.   B USB2ANY Firmware Upgrade
  10.   C Revision History

3.3 SYSREF Delay Generators

In generator modes, the SYSREF can be delayed by picosecond-size steps to more closely meet setup and hold requirements for high-frequency clock outputs. A delay divider, SYSREF_DLY_DIV, generates the interpolator frequency fINTERPOLATOR, which is usually in the range of 400 MHz to 800 MHz. This interpolator frequency is further subdivided into 512 delay codes, allowing approximately 2.5-ps to 5-ps delay steps across most of the CLKIN frequency range.

Each channel has its own delay codes which can be entered. The delay code algorithm is documented in the data sheet. To simplify delay calculation, the GUI provides an estimated relative delay: enter the relative delay, and the GUI will calculate the correct step values to achieve the requested delay as closely as possible. Alternately, the register-based delay fields can be stepped through or programmed to achieve the same result.

GUID-20210601-CA0I-NDHC-CZ1G-BQTSVHRFZ5CF-low.pngFigure 3-7 SYSREF Delay, in 5-Code Steps