SNAU266A July   2021  – August 2022

 

  1.   Abstract
  2. 1First-Time Setup
    1. 1.1 Evaluation Module Contents
    2. 1.2 Evaluation Setup Requirements
  3. 2EVM Connections
    1. 2.1 Connection Diagram
    2. 2.2 Power Supply
    3. 2.3 Reference Clock
    4. 2.4 Output Connections
    5. 2.5 Programming Interface
  4. 3Feature Evaluation
    1. 3.1 Buffer, Divider, and Multiplier Modes
    2. 3.2 SYSREF Generation
    3. 3.3 SYSREF Delay Generators
  5. 4Schematic
  6. 5PCB Layout and Layer Stack-Up
    1. 5.1 PCB Layer Stack-Up
    2. 5.2 PCB Layout
  7. 6Bill of Materials
  8.   A Troubleshooting
  9.   B USB2ANY Firmware Upgrade
  10.   C Revision History

1.2 Evaluation Setup Requirements

At a minimum, evaluation of the buffer mode requires:

  • A DC power supply capable of 3.3 V, 2 A
  • A high-quality signal source, such as an SMA100B
  • A spectrum analyzer or signal analyzer
  • A PC with a USB port, running Windows 7 or a more recent version of Windows
  • Texas Instruments Clocks and Synthesizers TICS Pro software

Full evaluation requires the following additional hardware:

  • A high-speed 4-CH oscilloscope capable of resolving 5-ps step size for SYSREF delay tuning
  • A 2-CH arbitrary function generator or other pulse source capable of outputting complementary LVDS pulses and DC levels (1.25 V ± 0.2 V, differential, into 100-Ω DC load) for triggering SYSREF, SYNCing the dividers, and determining SYSREF windowing values
  • A phase noise analysis system capable of measuring at up to 12.8 GHz